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Am186TMCC
High-Performance, 80C186-Compatible 16-Bit Embedded Communications Controller
DISTINCTIVE CHARACTERISTICS
n E86TM family of x86 embedded processors offers improved time-to-market - Software migration (backwards- and upwardscompatible) - World-class development tools, applications, and system software n Serial Communications Peripherals - Four High-level Data Link Control (HDLC) channels - Four independent Time Slot Assigners (TSAs) - Physical interface for HDLC channels can be raw DCE, PCM Highway, or GCI (IOM-2) - USB peripheral controller - High-Speed UART with autobaud - UART - Synchronous serial interface (SSI) - SmartDMATM channels (8) to support USB/HDLC n System Peripherals - Three programmable 16-bit timers - Hardware watchdog timer - General-purpose DMA (4 channels) - Programmable I/O (48 PIO signals) - Interrupt Controller (36 maskable interrupts) n Memory and Peripheral Interface - Integrated DRAM controller - Glueless interface to RAM/ROM/Flash memory (55-ns Flash memory required for zero-wait-state operation at 50 MHz) - Fourteen chip selects (8 peripherals, 6 memory) - External bus mastering support - Multiplexed and nonmultiplexed address/data bus - Programmable bus sizing - 8-bit boot option n Available in the following package - 160-pin plastic quad flat pack (PQFP) - 25-, 40-, and 50-MHz operating frequencies - Low-voltage operation, VCC = 3.3 V 0.3 V - Commercial and industrial temperature rating - 5-V-tolerant I/O (3.3-V output levels)
GENERAL DESCRIPTION
T h e A m 1 8 6 TM C C e m b e d d e d c o m mu n i c a t i o n s controller is the first member in the AMD Comm86TM product family. The AM186CC controller is a costeffective, high-performance microcontroller solution for communications applications. This highly integrated microcontroller enables customers to save system costs and increase perfor mance over 8-bit microcontrollers and other 16-bit microcontrollers. The AM186CC communications controller offers the advantages of the x86 development environment's widely available native development tools, applications, and system software. Additionally, the controller uses the industry-standard 186 instruction set that is part of the AMD E86TM family, which continually offers instruction-set-compatible upgrades. Built into the AM186CC controller is a wide range of communications features required in many communications applications, including High-level Data Link Control (HDLC) and the Universal Serial Bus (USB). AMD offers complete solutions with the AM186CC controller. A customer development platform board is available. Reference designs under development include a low-end router with Integrated Services Digital Network (ISDN), Ethernet, USB, Plain Old Telephone Service (POTS), and an ISDN Terminal Adapter featuring USB. AMD and its FusionE86SM Partners offer boards, schematics, drivers, protocol stacks, and routing software for these reference designs to enable fast time to market.
(c) Copyright 2000 Advanced Micro Devices, Inc. All rights reserved.
Publication# 21915 Rev: B Amendment/0 Issue Date: May 2000
ORDERING INFORMATION
AM186CC -50 K C \W LEAD FORMING \W=Trimmed and Formed TEMPERATURE RANGE C= AM186CC Commercial (TC =0C to +100C) I = AM186CC Industrial (TA =-40C to +85C) where: TC = case temperature where: TA = ambient temperature PACKAGE TYPE K=160-Pin Plastic Quad Flat Pack (PQFP) SPEED OPTION -25 = 25 MHz -40 = 40 MHz -50 = 50 MHz DEVICE NUMBER/DESCRIPTION AM186CC high-performance 80C186-compatible 16-bit embedded communications controller
Valid Combinations AM186CC-25 AM186CC-40 AM186CC-50 AM186CC-25 AM186CC-40 KI\W KC\W
Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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Am186TMCC Communications Controller Data Sheet
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 1 Ordering Information .................................................................................................................... 2 Logic Diagram by Interface .......................................................................................................... 6 Logic Diagram by Default Pin Function ....................................................................................... 7 Pin Connection Diagram--160-Pin PQFP Package .................................................................... 8 Pin and Signal Tables .................................................................................................................. 9 Signal Descriptions ............................................................................................................... 13 Architectural Overview ............................................................................................................... 28 Detailed Description .............................................................................................................. 28 Am186 Embedded CPU ........................................................................................................ 29 Memory Organization ............................................................................................................ 29 I/O Space .............................................................................................................................. 29 Serial Communications Support ............................................................................................ 30 Universal Serial Bus ......................................................................................................... 30 Four HDLC Channels and Four TSAs.............................................................................. 31 General Circuit Interface .................................................................................................. 31 Eight SmartDMATM Channels........................................................................................... 31 Two Asynchronous Serial Ports ....................................................................................... 31 Synchronous Serial Port................................................................................................... 32 System Peripherals ............................................................................................................... 32 Interrupt Controller ........................................................................................................... 32 Four General-Purpose DMA Channels ............................................................................ 32 48 Programmable I/O Signals .......................................................................................... 32 Three Programmable Timers ........................................................................................... 32 Hardware Watchdog Timer .............................................................................................. 33 Memory and Peripheral Interface .......................................................................................... 33 System Interfaces............................................................................................................. 33 DRAM Support ................................................................................................................. 34 Chip Selects ..................................................................................................................... 34 Clock Control ......................................................................................................................... 35 In-Circuit Emulator Support ................................................................................................... 37 Applications ............................................................................................................................... 37 Clock Generation and Control ................................................................................................... 40 Features ................................................................................................................................ 40 System Clock ........................................................................................................................ 40 USB Clock ............................................................................................................................. 40 Clock Sharing by System and USB ....................................................................................... 41 Crystal-Driven Clock Source ................................................................................................. 42 External Clock Source ........................................................................................................... 43 Static Operation .................................................................................................................... 43 PLL Bypass Mode ................................................................................................................. 43 UART Baud Clock ................................................................................................................. 43 Power Supply Operation ............................................................................................................ 44 Power Supply Connections ................................................................................................... 44 Input/Output Circuitry ............................................................................................................ 44 PIO Supply Current Limit ...................................................................................................... 44 Absolute Maximum Ratings ....................................................................................................... 45 Operating Ranges ...................................................................................................................... 45 Driver Characteristics--Universal Serial Bus ............................................................................ 45 DC Characteristics over Commercial and Industrial Operating Ranges .................................... 46 Capacitance ............................................................................................................................... 46
Am186TMCC Communications Controller Data Sheet
3
Maximum Load Derating ............................................................................................................ 47 Power Supply Current ................................................................................................................ 47 Thermal Characteristics ............................................................................................................. 48 PQFP Package ..................................................................................................................... 48 Commercial and Industrial Switching Characteristics and Waveforms ...................................... 49 Switching Characteristics over Commercial and Industrial Operating Ranges ......................................58 Appendix A--Pin Tables ............................................................................................................A-1 Pin List Table Column Definitions ......................................................................................A-11 Appendix B--Physical Dimensions: PQR160, Plastic Quad Flat Pack (PQFP) ........................B-1 Appendix C--Customer Support ...............................................................................................C-1 Related AMD Products--E86TM Family Devices ..................................................................C-1 Related Documents ..............................................................................................................C-2 AM186CC/CH/CU Microcontroller Customer Development Platform ..................................C-2 Third-Party Development Support Products .................................................................................C-2 Customer Service .................................................................................................................C-2 Hotline and World Wide Web Support............................................................................. C-2 Corporate Applications Hotline........................................................................................ C-2 World Wide Web Home Page ......................................................................................... C-3 Documentation and Literature ......................................................................................... C-3 Literature Ordering .......................................................................................................... C-3 Index ................................................................................................................................... Index-1
LIST OF FIGURES
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. AM186CC Controller Block Diagram ..................................................................... 28 Two-Component Address Example ...................................................................... 30 AM186CC Controller Address Bus -- Default Operation ...................................... 35 AM186CC Controller--Address Bus Disable In Effect .......................................... 36 ISDN Terminal Adapter System Application ......................................................... 38 ISDN to Ethernet Low-End Router System Application ........................................ 38 32-Channel Linecard System Application ............................................................. 39 System and USB Clock Generation ...................................................................... 41 Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies . 42 External Interface to Support Clocks--Fundamental Mode Crystal ...................... 42 External Interface to Support Clocks--External Clock Source ............................. 43 UART and High-Speed UART Clocks ................................................................... 43 Typical Icc Versus Frequency ................................................................................ 47 Thermal Resistance(C/Watt) ............................................................................... 48 Thermal Characteristics Equations ....................................................................... 48 Key to Switching Waveforms ................................................................................ 49 Read Cycle Waveforms ........................................................................................ 60 Write Cycle Waveforms ......................................................................................... 63 Software Halt Cycle Waveforms ........................................................................... 64 Peripheral Timing Waveforms ............................................................................... 65 Reset Waveforms .................................................................................................. 66 Signals Related to Reset (System PLL in 1x or 2x Mode) .................................... 67 Signals Related to Reset (System PLL in 4x Mode) ............................................. 67 Synchronous Ready Waveforms ........................................................................... 68 Asynchronous Ready Waveforms ......................................................................... 69 Entering Bus Hold Waveforms .............................................................................. 70 Exiting Bus Hold Waveforms ................................................................................. 70 System Clock Timing Waveforms--Active Mode (PLL 1x Mode) ......................... 72 USB Clock Timing Waveforms .............................................................................. 72 GCI Bus Waveforms ............................................................................................. 73
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Am186TMCC Communications Controller Data Sheet
Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
PCM Highway Waveforms (Timing Slave) ............................................................ 75 PCM Highway Waveforms (Timing Master) .......................................................... 76 DCE Transmit Waveforms .................................................................................... 77 DCE Receive Waveforms ..................................................................................... 77 USB Data Signal Rise and Fall Times .................................................................. 78 USB Receiver Jitter Tolerance .............................................................................. 78 Synchronous Serial Interface Waveforms ............................................................. 79 DRAM Read Cycle without Wait-States Waveform ............................................... 80 DRAM Read Cycle with Wait-States Waveform .................................................... 81 DRAM Write Cycle without Wait-States Waveform ............................................... 81 DRAM Write Cycle with Wait-States Waveform .................................................... 82 DRAM Refresh Cycle Waveform ........................................................................... 82
LIST OF TABLES
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. PQFP Pin Assignments--Sorted by Pin Number .................................................. 10 PQFP Pin Assignments--Sorted by Signal Name ................................................ 11 Signal Description Table Definitions ...................................................................... 13 Signal Descriptions ............................................................................................... 14 Segment Register Selection Rules ....................................................................... 30 Crystal Parameters ................................................................................................ 42 Typical Power Consumption Calculation................................................................ 47 Thermal Characteristics (C/Watt) ........................................................................ 48 Alphabetical Key to Switching Parameter Symbols .............................................. 50 Numerical Key to Switching Parameter Symbols .................................................. 54 Read Cycle Timing ................................................................................................ 58 Write Cycle Timing ................................................................................................ 61 Software Halt Cycle Timing ................................................................................... 64 Peripheral Timing .................................................................................................. 65 Reset Timing ......................................................................................................... 66 External Ready Cycle Timing ................................................................................ 68 Bus Hold Timing .................................................................................................... 69 System Clocks Timing ........................................................................................... 71 USB Clocks Timing ............................................................................................... 72 GCI Bus Timing ..................................................................................................... 73 PCM Highway Timing (Timing Slave) ................................................................... 74 PCM Highway Timing (Timing Master) ................................................................. 76 DCE Interface Timing ............................................................................................ 77 USB Timing ........................................................................................................... 78 SSI Timing ............................................................................................................. 79 DRAM Timing ........................................................................................................ 80 Power-On Reset (POR) Pin Defaults ...................................................................A-2 Multiplexed Signal Trade-offs ...............................................................................A-5 PIOs Sorted by PIO Number ................................................................................A-8 PIOs Sorted by Signal Name ...............................................................................A-9 Reset Configuration Pins (Pinstraps) .................................................................A-10 CPU PLL Modes .................................................................................................A-10 USB PLL Modes..................................................................................................A-10 Pin List Table Definitions.....................................................................................A-11 Pin List Summary ...............................................................................................A-12
Am186TMCC Communications Controller Data Sheet
5
LOGIC DIAGRAM BY INTERFACE1
Reset/ Clocks
CLKOUT RES RESOUT X1 X2
20
INT8-INT0 NMI LCS MCS3-MCS0 PCS7-PCS0 UCS
9
/
Interrupts
4 8
/ /
Chip Selects
Address and Address/Data Buses
A19-A0 AD15-AD0 ALE ARDY BHE BSIZE8 DEN DS DRQ1-DRQ0 DT/R HLDA HOLD RD S2-S0 S6 SRDY WHB WLB WR PWD TMRIN1-TMRIN0 TMROUT1-TMROUT0 QS1-QS0 SDEN SCLK SDATA RXD_U TXD_U CTS_U RTR_U RXD_HU TXD_HU CTS_HU RTR_HU UCLK PIO47-PIO0
16
CAS0 CAS1 RAS0 RAS1 DCE_RXD_A, B, C, D DCE_TXD_A, B, C, D DCE_RCLK_A, B, C, D DCE_TCLK_A, B, C, D DCE_CTS_A, B, C, D DCE_RTR_A, B, C, D PCM_RXD_A, B, C, D PCM_TXD_A, B, C, D PCM_CLK_A, B, C, D PCM_FSC_A, B, C, D PCM_TSC_A, B, C, D GCI_DD_A GCI_DU_A GCI_DCL_A GCI_FSC_A USBD+ USBD- USBSCI USBSOF USBX1 USBX2 UDMNS UDPLS UTXDMNS UTXDPLS UXVOE UXVRCV {ADEN} {CLKSEL1} {CLKSEL2} {ONCE} {UCSX8} {USBSEL1} {USBSEL2} {USBXCVR}
4 4
DRAM Control
/
/
2
/
Bus Status and Control
3
/ / 4 / 4 /
4 4 4
4
DCE Interface (HDLC A-D)1
/
/
/
4 4
/ / 4 /
PCM Interface (HDLC A-D)1
Programmable Timers Debug Synchronous Serial Interface
2
/ / /
GCI Interface (HDLC A)1
2
2
Universal Serial Bus (USB)
Asynchronous Serial Interface (UART)
USB External Transceiver Interface
High-Speed UART
UART Clock Programmable I/O (PIO)
Configuration Pinstraps
Notes: 1. Because of multiplexing, not all interfaces are available at once. Refer to Table 28, "Multiplexed Signal Trade-offs," on page A-5.
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Am186TMCC Communications Controller Data Sheet
LOGIC DIAGRAM BY DEFAULT PIN FUNCTION1
Reset/ Clocks
CLKOUT RES RESOUT X1 X2
20 16
DCE_RXD_A [GCI_DD_A] [PCM_RXD_A] DCE_TXD_A [GCI_DU_A] [PCM_TXD_A] DCE_RCLK_A [GCI_DCL_A] [PCM_CLK_A] DCE_TCLK_A [GCI_FSC_A] [PCM_FSC_A]
HDLC A (DCE)
Address and Address/Data Buses
A19-A0 AD15-AD0 ALE [PIO33] ARDY [PIO8] BHE [PIO34] {ADEN} BSIZE8 DEN [DS] [PIO30] DRQ1 DT/R [PIO29] HLDA {CLKSEL1} HOLD RD S0 {USBXCVR} S1 S2 S6 SRDY [PIO35] WHB WLB WR [PIO15] PIO0 [TMRIN1] PIO1 [TMROUT1] PIO2 [PCS5] PIO3 [PCS4] {CLKSEL2} PIO4 [MCS0] {UCSX8} PIO5 [MCS3] [RAS1] PIO6 [INT8] [PWD] PIO7 [INT7] PIO8 [ARDY] PIO9 [DRQ0] PIO10 [SDEN] PIO11 [SCLK] PIO12 [SDATA]
Programmable I/O (PIO)
Bus Status and Control
Debug High-Speed UART
Chip Selects
Universal Serial Bus (USB)
6
Interrupts
/
No Connection
PIO16 [RXD_HU] PIO17 [DCE_CTS_A] [PCM_TSC_A] PIO18 [DCE_RTR_A] PIO19 [INT6] PIO20 [TXD_U] [DCE_TXD_D] [PCM_TXD_D] QS1-QS0 PIO21 [UCLK] [USBSOF] [USBSCI] PIO22 [DCE_RCLK_C] [PCM_CLK_C] TXD_HU PIO23 [DCE_TCLK_C] [PCM_FSC_C] PIO24 [CTS_U] [DCE_TCLK_D] [PCM_FSC_D] LCS [RAS0] PIO25 [RTR_U] [DCE_RCLK_D] [PCM_CLK_D] PIO26 [RXD_U] [DCE_RXD_D] [PCM_RXD_D] MCS1 [CAS1] PIO27 [TMRIN0] MCS2 [CAS0] PIO28 [TMROUT0] PCS0 [PIO13] {USBSEL1} PCS1 [PIO14] {USBSEL2} PIO31 [PCS7] PCS2 PIO32 [PCS6] PCS3 UCS {ONCE} PIO36 [DCE_RXD_B] [PCM_RXD_B] USBD+ [UDPLS] PIO37 [DCE_TXD_B] [PCM_TXD_B] USBD- [UDMNS] PIO38 [DCE_CTS_B] [PCM_TSC_B] USBX1 PIO39 [DCE_RTR_B] USBX2 PIO40 [DCE_RCLK_B] [PCM_CLK_B] PIO41 [DCE_TCLK_B] [PCM_FSC_B] INT5-INT0 PIO42 [DCE_RXD_C] [PCM_RXD_C] NMI PIO43 [DCE_TXD_C] [PCM_TXD_C] PIO44 [DCE_CTS_C] [PCM_TSC_C] PIO45 [DCE_RTR_C] PIO46 [CTS_HU] [DCE_CTS_D] [PCM_TSC_D] PIO47 [RTR_HU] [DCE_RTR_D] RSVD_104 [UXVRCV] RSVD_103 [UXVOE] RSVD_102 [UTXDMNS] RSVD_101 [UTXDPLS]
Notes:
1. Pin names in bold indicate the default pin function. Brackets, [ ], indicate alternate, multiplexed functions. Braces, { }, indicate pinstrap pins.
Am186TMCC Communications Controller Data Sheet
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8
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 VCC TXD_U/DCE_TXD_D/PCM_TXD_D RXD_U/DCE_RXD_D/PCM_RXD_D CTS_U/DCE_TCLK_D/PCM_FSC_D RTR_U/DCE_RCLK_D/PCM_CLK_D VSS DCE_TXD_C/PCM_TXD_C DCE_RXD_C/PCM_RXD_C DCE_CTS_C/PCM_TSC_C DCE_RTR_C DCE_RCLK_C/PCM_CLK_C DCE_TCLK_C/PCM_FSC_C VCC INT8/PWD INT7 INT6 TMRIN1 TMROUT1 TMRIN0 TMROUT0 VSS DCE_TXD_B/PCM_TXD_B DCE_RXD_B/PCM_RXD_B DCE_CTS_B/PCM_TSC_B DCE_RTR_B DCE_RCLK_B/PCM_CLK_B DCE_TCLKB/PCM_FSC_B VCC UCS {ONCE} LCS/RAS0 VSS MCS3/RAS1 MCS2/CAS0 MCS1/CAS1 MCS0 {UCSX8} VCC DRQ0 DCE_CTS_A/PCM_TSC_A DCE_RTR_A VSS
PIN CONNECTION DIAGRAM--160-PIN PQFP PACKAGE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VSS SDEN SCLK SDATA PCS0 {USBSEL1} PCS1 {USBSEL2} PCS2 PCS3 PCS4 {CLKSEL2} PCS5 PCS6 VCC PCS7 ARDY SRDY WR DT/R DEN/DS ALE BHE {ADEN} VSS UCLK/USBSOF/USBSCI RTR_HU/DCE_RTR_D CTS_HU/DCE_CTS_D/PCM_TSC_D RXD_HU TXD_HU VCC AD0 AD8 A0 A1 A2 VSS AD1 AD9 A3 A4 AD2 AD10 VCC
Am186TMCC Communications Controller Data Sheet
VCC DCE_TXD_A/GCI_DU_A/PCM_TXD_A DCE_RXD_A/GCI_DD_A/PCM_RXD_A DCE_RCLK_A/GCI_DCL_A/PCM_CLK_A DCE_TCLK_A/GCI_FSC_A/PCM_FSC_A NMI RES INT5 INT4 INT3 INT2 INT1 VSS INT0 VCC DRQ1 RSVD_104/UXVRCV RSVD_103/UXVOE RSVD_102/UTXDMNS RSVD_101/UTXDPLS VSS HOLD HLDA {CLKSEL1} RD WLB WHB BSIZE8 AD15 AD7 VCC A19 A18 A17 AD14 AD6 A16 A15 VSS VSS_USB USBD+/UDPLS
VSS A5 A6 A7 A8 AD3 AD11 VCC A9 A10 AD4 AD12 VSS S6 S2 S1 S0 {USBXCVR} RESOUT VCC CLKOUT VSS QS0 QS1 A11 A12 AD5 AD13 VCC A13 A14 VSS VSS_A X1 X2 USBX1 USBX2 VCC_A VCC VCC_USB USBD-/UDMNS
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PIN AND SIGNAL TABLES
Table 1 on page 10 and Table 2 on page 11 show the pi n s s o r t ed by pi n nu mb e r a nd s i g na l n a me, respectively. Table 4 on page 14 contains the signal descriptions (grouped alphabetically and by function). The table includes columns listing the multiplexed functions and I/O type. Table 3 on page 13 shows terms used in Table 4. Refer to Appendix A, "Pin Tables," on page A-1 for an a d d i ti on a l gr o u p o f t a bl e s w i th t h e f o l l ow i n g information: n Power-on reset (POR) pin defaults including pin numbers and multiplexed functions--Table 27 on page A-2. n Multiplexed page A-5. signal trade-offs--Table 28 on n Programmable I/O (PIO) pins ordered by PIO pin number and multiplexed signal name, respectively, including columns listing multiplexed functions and pin configurations following system reset--Table 29 on page A-8 and Table 30 on page A-9. n Pinstraps and page A-10. pinstrap options--Table 31 on
n Pin and signal summary showing signal name and alternate function, pin number, I/O type, load values, POR default function, reset state, POR default operation, hold state, and voltage--Table 35 on page A-12. In all tables the brackets, [ ], indicate alternate, multiplexed functions, and braces, { }, indicate reset configuration pins (pinstraps). The line over a pin name indicates an active Low. The word pin refers to the physical wire; the word signal refers to the electrical signal that flows through it.
Am186TMCC Communications Controller Data Sheet
9
Table 1. PQFP Pin Assignments--Sorted by Pin Number1
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Name--Left Side
VSS SDEN SCLK SDATA PCS0 {USBSEL1} PCS1 {USBSEL2} PCS2 PCS3 PCS4 {CLKSEL2} PCS5 PCS6 VCC PCS7 ARDY SRDY WR DT/R DEN/DS ALE BHE {ADEN} VSS UCLK/USBSOF/USBSCI RTR_HU/DCE_RTR_D CTS_HU/DCE_CTS_D/ PCM_TSC_D RXD_HU TXD_HU VCC AD0 AD8 A0 A1 A2 VSS AD1 AD9 A3
Pin No. Name--Bottom Side Pin No.
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 VSS A5 A6 A7 A8 AD3 AD11 VCC A9 A10 AD4 AD12 VSS S6 S2 S1 S0 {USBXCVR} RESOUT VCC CLKOUT VSS QS0 QS1 A11 A12 AD5 AD13 VCC A13 A14 VSS VSS_A X1 X2 USBX1 USBX2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116
Name--Right Side
USBD+/UDPLS VSS_USB VSS A15 A16 AD6 AD14 A17 A18 A19 VCC AD7 AD15 BSIZE8 WHB WLB RD HLDA {CLKSEL1} HOLD VSS RSVD_101/UTXDPLS RSVD_102/UTXDMNS RSVD_103/UXVOE RSVD_104/UXVRCV DRQ1 VCC INT0 VSS INT1 INT2 INT3 INT4 INT5 RES NMI DCE_TCLK_A/ GCI_FSC_A/ PCM_FSC_A DCE_RCLK_A / GCI_DCL_A/ PCM_CLK_A
Pin No.
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Name--Top Side
VSS DCE_RTR_A DCE_CTS_A/ PCM_TSC_A DRQ0 VCC MCS0 {UCSX8} MCS1/CAS1 MCS2/CAS0 MCS3/RAS1 VSS LCS/RAS0 UCS {ONCE} VCC DCE_TCLK_B/ PCM_FSC_B DCE_RCLK_B/ PCM_CLK_B DCE_RTR_B DCE_CTS_B/ PCM_TSC_B DCE_RXD_B/ PCM_RXD_B DCE_TXD_B/ PCM_TXD_B VSS TMROUT0 TMRIN0 TMROUT1 TMRIN1 INT6 INT7 INT8/PWD VCC DCE_TCLK_C/ PCM_FSC_C DCE_RCLK_C/ PCM_CLK_C DCE_RTR_C DCE_CTS_C/ PCM_TSC_C DCE_RXD_C/ PCM_RXD_C DCE_TXD_C/ PCM_TXD_C VSS RTR_U/ DCE_RCLK_D/ PCM_CLK_D CTS_U/ DCE_TCLK_D/ PCM_FSC_D
37
A4
77
VCC_A
117
157
10
Am186TMCC Communications Controller Data Sheet
Table 1. PQFP Pin Assignments--Sorted by Pin Number1 (Continued)
Pin No.
38 39 40
Name--Left Side
AD2 AD10 VCC
Pin No. Name--Bottom Side Pin No.
78 79 80 VCC VCC_USB USBD-/UDMNS 118 119 120
Name--Right Side
DCE_RXD_A/GCI_DD_A/ PCM_RXD_A DCE_TXD_A/GCI_DU_A/ PCM_TXD_A VCC
Pin No.
158 159 160
Name--Top Side
RXD_U/DCE_RXD_D/ PCM_RXD_D TXD_U/DCE_TXD_D/ PCM_TXD_D VCC
Notes: 1. See Table 29, "PIOs Sorted by PIO Number," on page A-8 for PIOs sorted by PIO number.
Table 2. PQFP Pin Assignments--Sorted by Signal Name1
Signal Name
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10
Pin No. Signal Name
30 31 32 36 37 42 43 44 45 49 50 64 65 69 70 84 85 88 89 90 28 34 38 46 51 66 86 92 29 35 39 CLKOUT CTS_HU/DCE_CTS_D/ PCM_TSC_D CTS_U/DCE_TCLK_D/ PCM_FSC_D DCE_CTS_A/PCM_TSC_A DCE_CTS_B/ PCM_TSC_B DCE_CTS_C/PCM_TSC_C DCE_RCLK_A/ GCI_DCL_A/PCM_CLK_A DCE_RCLK_B/ PCM_CLK_B DCE_RCLK_C/PCM_CLK_C DCE_RTR_A DCE_RTR_B DCE_RTR_C DCE_RXD_A/GCI_DD_A/ PCM_RXD_A DCE_RXD_B/ PCM_RXD_B DCE_RXD_C/ PCM_RXD_C DCE_TCLK_A/ GCI_FSC_A/PCM_FSC_A DCE_TCLK_B/ PCM_FSC_B DCE_TCLK_C/ PCM_FSC_C DCE_TXD_A/GCI_DU_A/ PCM_TXD_A DCE_TXD_B/ PCM_TXD_B DCE_TXD_C/ PCM_TXD_C DEN/DS DRQ0 DRQ1 DT/R HLDA {CLKSEL1} HOLD INT0 INT1 INT2 INT3
Pin No.
60 24 157 123 137 152 117 135 150 122 136 151 118 138 153 116 134 149 119 139 154 18 124 105 17 98 99 107 109 110 111
Signal Name
MCS3/RAS1 NMI PCS0 {USBSEL1} PCS1 {USBSEL2} PCS2 PCS3 PCS4 {CLKSEL2} PCS5 PCS6 PCS7 QS0 QS1 RD RES RESOUT RSVD_104/UXVRCV RSVD_103/UXVOE RSVD_102/UTXDMNS RSVD_101/UTXDPLS RTR_HU/DCE_RTR_D RTR_U/DCE_RCLK_D/ PCM_CLK_D RXD_HU RXD_U/DCE_RXD_D/ PCM_RXD_D S0 {USBXCVR} S1 S2 S6 SCLK SDATA SDEN SRDY
Pin No. Signal Name
129 115 5 6 7 8 9 10 11 13 62 63 97 114 58 104 103 102 101 23 156 25 158 57 56 55 54 3 4 2 15 USBD-/UDMNS USBX1 USBX2 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_A VCC_USB VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Pin No.
80 75 76 12 27 40 48 59 68 78 91 106 120 125 133 148 160 77 79 1 21 33 41 53 61 71 83 100 108 121 130
Am186TMCC Communications Controller Data Sheet
11
Table 2. PQFP Pin Assignments--Sorted by Signal Name 1 (Continued)
Signal Name
AD11 AD12 AD13 AD14 AD15 ALE ARDY BHE {ADEN} BSIZE8
Pin No. Signal Name
47 52 67 87 93 19 14 20 94 INT4 INT5 INT6 INT7 INT8/PWD LCS/RAS0 MCS0 {UCSX8} MCS1/CAS1 MCS2/CAS0
Pin No.
112 113 145 146 147 131 126 127 128
Signal Name
TMRIN0 TMRIN1 TMROUT0 TMROUT1 TXD_HU TXD_U/DCE_TXD_D/ PCM_TXD_D UCLK/USBSOF/USBSCI UCS {ONCE} USBD+/UDPLS
Pin No. Signal Name
142 144 141 143 26 159 22 132 81 VSS V SS V SS_A V SS_USB WHB WLB WR X1 X2
Pin No.
140 155 72 82 95 96 16 73 74
Notes: 1. For PIOs sorted by signal name, refer to Table 30, "PIOs Sorted by Signal Name," on page A-9.
12
Am186TMCC Communications Controller Data Sheet
Signal Descriptions
Table 4 on page 14 contains a description of the AM186CC controller signals. Table 3 describes the terms used in Table 4. The signals are organized alphabetically within the following functional groups: n Bus interface/general-purpose DMA request (page 14) n Clocks/reset/watchdog timer (page 17) n No connects (page 18) n Power and ground (page 19) n Debug support (page 19) n Chip selects (page 19) n DRAM (page 20) n Interrupts (page 21) n Programmable I/O (PIOs) (page 22) n Programmable timers (page 22) n Asynchronous serial ports (UART and High-Speed UART) (page 22) n Synchronous serial interface (SSI) (page 23) n HDLC synchronous communications: channels A-D for Data Communications Equipment (DCE), Pulse-Code Modulation (PCM), and General Circuit Interface (GCI) interfaces (page 23) n Universal serial bus (USB) (page 26) For pinstraps, refer to Table 31, "Reset Configuration Pins (Pinstraps)," on page A-10.
Table 3.
Term [] {} pin reset
Signal Description Table Definitions
Definition Pin alternate function; a pin defaults to the signal named without the brackets Reset configuration pin (pinstrap) Refers to the physical wire An external or power-on reset is caused by asserting RES. An internal reset is initiated by the watchdog timer. A system reset is one that resets the AM186CC controller (the CPU plus the internal peripherals) as well as any external peripherals connected to RESOUT. An external reset always causes a system reset; an internal reset can optionally cause a system reset. Refers to the electrical signal that flows across a pin A line over a signal name indicates that the signal is active Low; a signal name without a line is active High. Bidirectional High Programmable to hold last state of pin Totem pole output Open drain output Open drain output or totem pole output Internal pulldown resistor Internal pullup resistor Schmitt trigger Input Schmitt trigger input or open drain output Three-state output
General terms
signal SIGNAL
Signal types B H LS O OD OD-O PD PU STI STI-OD TS
Am186TMCC Communications Controller Data Sheet
13
Table 4.
Signal Name Multiplexed Signal(s) --
Signal Descriptions
Type Description
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST A19-A0 O Address Bus supplies nonmultiplexed memory or I/O addresses to the system one half of a CLKOUT period earlier than the multiplexed address and data bus (AD15-AD0). During bus-hold or reset conditions, the address bus is threestated with pulldowns. When the lower or upper chip-select regions are configured for DRAM mode, the A19-A0 bus provides the row and column addresses at the appropriate times. The upper and lower memory chip-select ranges can be individually configured for DRAM mode. AD15-AD0 -- B Address and Data Bus time-multiplexed pins supply memory or I/O addresses and data to the system. This bus can supply an address to the system during the first period of a bus cycle (t1). It transmits (write cycle) or receives (read cycle) data to or from the system during the remaining periods of that cycle (t2, t3, and t4). The address phase of these pins can be disabled--see the {ADEN} pin description in Table 31, "Reset Configuration Pins (Pinstraps)," on page A-10. During a reset condition, the address and data bus is three-stated with pulldowns, and during a bus hold it is three-stated. In addition, during a reset the state of the address and data bus pins (AD15- AD0) is latched into the Reset Configuration (RESCON) register. This feature can be used to provide software with information about the external system at reset time. ALE [PIO33] O Address Latch Enable indicates to the system that an address appears on the address and data bus (AD15-AD0). The address is guaranteed valid on the falling edge of ALE. ALE is three-stated and has a pulldown resistor during bus-hold or reset conditions. ARDY [PIO8] STI Asynchronous Ready is a true asynchronous ready that indicates to the AM186CC controller that the addressed memory space or I/O device will complete a data transfer. The ARDY pin is asynchronous to CLKOUT and is active High. To guarantee the number of wait states inserted, ARDY or SRDY must be synchronized to CLKOUT. If the falling edge of ARDY is not synchronized to CLKOUT as specified, an additional clock period can be added. To always assert the ready condition to the microcontroller, tie ARDY and SRDY High. If the system does not use ARDY, tie the pin Low to yield control to SRDY.
14
Am186TMCC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name BHE Multiplexed Signal(s) [PIO34] {ADEN} Type Description O Bus High Enable: During a memory access, BHE and the least-significant address bit (AD0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The BHE and AD0 pins are encoded as follows: Data Byte Encoding BHE 0 0 1 1 AD0 0 1 0 1 Type of Bus Cycle Word transfer High byte transfer (bits 15-8) Low byte transfer (bits 7-0) Refresh
BHE is asserted during t1 and remains asserted through t3 and tW. BHE does not require latching. BHE is three-stated with a pullup during bus-hold and reset conditions. WLB and WHB implement the functionality of BHE and AD0 for high and low byte write enables, and they have timing appropriate for use with the nonmultiplexed bus interface. BHE also signals DRAM refresh cycles when using the multiplexed address and data (AD) bus. A refresh cycle is indicated when both BHE and AD0 are High. During refresh cycles, the AD bus is driven during the t1 phase and three-stated during the t2, t3, and t4 phases. The value driven on the A bus is undefined during a refresh cycle. For this reason, the A0 signal cannot be used in place of the AD0 signal to determine refresh cycles. BSIZE8 DEN -- [DS] [PIO30] O O Bus Size 8 is asserted during t1-t4 to indicate an 8-bit cycle, or is deasserted to indicate a 16-bit cycle. Data Enable supplies an output enable to an external data-bus transceiver. DEN is asserted during memory and I/O cycles. DEN is deasserted when DT/R changes state. DEN is three-stated with a pullup during bus-hold or reset conditions. Data Strobe provides a signal where the write cycle timing is identical to the read cycle timing. When used with other control signals, [DS] provides an interface for 68K-type peripherals without the need for additional system interface logic. When [DS] is asserted, addresses are valid. When [DS] is asserted on writes, data is valid. When [DS] is asserted on reads, data can be driven on the AD bus. Following a reset, this pin is configured as DEN. The pin is then configured by software to operate as [DS]. DT/R [PIO29] O Data Transmit or Receive indicates which direction data should flow through an external data-bus transceiver. When DT/R is asserted High, the AM186CC controller transmits data. When this pin is deasserted Low, the controller receives data. DT/R is three-stated with a pullup during a bus-hold or reset condition. DMA Requests 1 and 0 indicate to the AM186CC controller that an external device is ready for a DMA channel to perform a transfer. DRQ1-[DRQ0] are level-triggered and internally synchronized. DRQ1-[DRQ0] are not latched and must remain active until serviced.
[DS]
DEN PIO30
O
DRQ1 [DRQ0]
-- PIO9
STI STI
Am186TMCC Communications Controller Data Sheet
15
Table 4. Signal Descriptions (Continued)
Signal Name HLDA Multiplexed Signal(s) {CLKSEL1} Type Description O Bus-Hold Acknowledge is asserted to indicate to an external bus master that the AM186CC controller has relinquished control of the local bus. When an external bus master requests control of the local bus (by asserting HOLD), the microcontroller completes the bus cycle in progress, then relinquishes control of the bus to the external bus master by asserting HLDA and three-stating S2-S0, AD15-AD0, S6, and A19-A0. The following are also three-stated and have pullups: UCS, LCS, MCS3-MCS0, PCS7-PCS0, DEN, RD, WR, BHE, WHB, WLB, and DT/R. ALE is three-stated and has a pulldown. When the external bus master has finished using the local bus, it indicates this to the AM186CC controller by deasserting HOLD. The controller responds by deasserting HLDA. If the AM186CC controller requires access to the bus (for example, for refresh), the controller deasserts HLDA before the external bus master deasserts HOLD. The external bus master must be able to deassert HOLD and allow the controller access to the bus. See the timing diagrams for bus hold on page 70. HOLD -- STI Bus-Hold Request indicates to the AM186CC controller that an external bus master needs control of the local bus. The AM186CC controller's HOLD latency time--the time between HOLD request and HOLD acknowledge--is a function of the activity occurring in the processor when the HOLD request is received. A HOLD request is second only to DRAM refresh requests in priority of activity requests received by the processor. This implies that if a HOLD request is received just as a DMA transfer begins, the HOLD latency can be as great as four bus cycles. This occurs if a DMA word transfer operation is taking place from an odd address to an odd address. This is a total of 16 clock cycles or more if wait states are required. In addition, if locked transfers are performed, the HOLD latency time is increased by the length of the locked transfer. HOLD latency is also potentially increased by DRAM refreshes. The board designer is responsible for properly terminating the HOLD input. For more information, see the HLDA pin description. RD -- O Read Strobe indicates to the system that the AM186CC controller is performing a memory or I/O read cycle. RD is guaranteed to not be asserted before the address and data bus is three-stated during the address-to-data transition. RD is three-stated with a pullup during bus-hold or reset conditions. Bus Cycle Status Bit 6: This signal is asserted during t 1-t4 to indicate a DMAinitiated bus cycle or a refresh cycle. S6 is three-stated during bus hold and three-stated with a pulldown during reset. Synchronous Ready indicates to the AM186CC controller that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active High input synchronized to CLKOUT. Using SRDY instead of ARDY allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ARDY. To always assert the ready condition to the microcontroller, tie SRDY High. If the system does not use SRDY, tie the pin Low to yield control to ARDY.
S6
--
O
SRDY
[PIO35]
STI
16
Am186TMCC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name S2 S1 S0 Multiplexed Signal(s) -- -- {USBXCVR} Bus Status Pins S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Bus Cycle Reserved Read data from I/O Write data to I/O Halt Instruction fetch Read data from memory Write data to memory None (passive) Type Description O Bus Cycle Status 2-0 indicate to the system the type of bus cycle in progress. S2 can be used as a logical memory or I/O indicator, and S1 can be used as a data transmit or receive indicator. S2-S0 are three-stated during bus hold and three-stated with a pullup during reset. The S2-S0 pins are encoded as follows:
WHB WLB
-- --
O O
Write High Byte and Write Low Byte indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 microcontroller designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WHB is asserted with AD15-AD8. WHB is the logical AND of BHE and WR. This pin is three-stated with a pullup during bus-hold or reset conditions. WLB is asserted with AD7-AD0. WLB is the logical AND of AD0 and WR. This pin is three-stated with a pullup during bus-hold or reset conditions.
WR
[PIO15]
O
Write Strobe indicates to the system that the data on the bus is to be written to a memory or I/O device. WR is three-stated with a pullup during bus-hold or reset conditions. Clock Output supplies the clock to the system. Depending on the values of the CPU mode select pinstraps, {CLKSEL1} and {CLKSEL2}, CLKOUT operates at either the PLL frequency or the source input frequency during PLL Bypass mode. (See Table 31, "Reset Configuration Pins (Pinstraps)," on page A-10.) CLKOUT remains active during bus-hold or reset conditions. The DISCLK bit in the SYSCON register can be set to disable the CLKOUT signal. Refer to the Am186TMCC/CH/CU Microcontrollers Register Set Manual (order #21916). All synchronous AC timing specifications not associated with SSI, HDLCs, UARTs, and the USB are synchronous to CLKOUT.
CLOCKS/RESET/WATCHDOG TIMER CLKOUT -- O
Am186TMCC Communications Controller Data Sheet
17
Table 4. Signal Descriptions (Continued)
Signal Name RES Multiplexed Signal(s) -- Type Description STI Reset requires the AM186CC controller to perform a reset. When RES is asserted, the controller immediately terminates its present activity, clears its internal logic, and on the deassertion of RES, transfers CPU control to the reset address FFFF0h. RES must be asserted for at least 1 ms to allow the internal circuits to stabilize. RES can be asserted asynchronously to CLKOUT because RES is synchronized internally. For proper initialization, VCC must be within specifications, and CLKOUT must be stable for more than four CLKOUT periods during which RES is asserted. If RES is asserted while the watchdog timer is performing a watchdog-timer reset, the external reset takes precedence over the watchdog-timer reset. This means that the RESOUT signal asserts as with any external reset and the WDTCON register will not have the RSTFLAG bit set. In addition, the controller will exit reset based on the external reset timing, i.e., 4.5 clocks after the deassertion of RES rather than 216 clocks after the watchdog timer timeout occurred. The AM186CC controller begins fetching instructions approximately 6.5 CLKOUT periods after RES is deasserted. This input is provided with a Schmitt trigger to facilitate power-on RES generation via an RC network. RESOUT -- O Reset Out indicates that the AM186CC controller is being reset (either externally or internally), and the signal can be used as a system reset to reset any external peripherals connected to RESOUT. During an external reset, RESOUT remains active (High) for two clocks after RES is deasserted. The controller exits reset and begins the first valid bus cycle approximately 4.5 clocks after RES is deasserted. [UCLK] [USBSOF] [USBSCI] PIO21 -- -- STI UART Clock can be used instead of the processor clock as the source clock for either the UART or the High-Speed UART. The source clock for the UART and the High-Speed UART are selected independently and both can use the same source. USB Controller Crystal Input (USBX1) and USB Controller Crystal Output (USBX2) provide connections for a fundamental mode, parallel-resonant crystal used by the internal USB oscillator circuit. If the CPU crystal is used to generate the USB clock, USBX1 must be pulled down. X1 X2 -- -- STI O CPU Crystal Input (X1) and CPU Crystal Output (X2) provide connections for a fundamental mode, parallel-resonant crystal used by the internal oscillator circuit. If an external oscillator is used, inject the signal directly into X1 and leave X2 floating.
USBX1 USBX2
STI O
PINSTRAPS (See Table 31, "Reset Configuration Pins (Pinstraps)," on page A-10.) RESERVED RSVD_101 RSVD_102 RSVD_103 RSVD_104 UTXDPLS UTXDMNS UXVOE UXVRCV -- -- -- -- RSVD_101-RSVD_104 are reserved unless pinstrap {USBXCVR} is sampled Low on the rising edge of RESET. When reserved, these pins should not be connected.
18
Am186TMCC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed Signal(s) -- -- -- -- -- -- -- Type Description
POWER AND GROUND VCC (15) VCC _A (1) VCC _USB (1) VSS (15) VSS _A (1) VSS _USB (1) QS1-QS0 STI STI STI STI STI STI O Digital Power Supply pins supply power (+3.3 0.3 V) to the AM186CC controller logic. Analog Power Supply pin supplies power (+3.3 0.3 V) to the oscillators and PLLs. USB Power Supply pin supplies power (+3.3 0.3 V) to the USB block. Digital Ground pins connect the AM186CC controller logic to the system ground. Analog Ground pin connects the oscillators and PLLs to the system ground. USB Ground pin connects the USB block to the system ground. Queue Status 1-0 values provide information to the system concerning the interaction of the CPU and the instruction queue. The pins have the following meanings: Queue Status Pins QS1 QS0 Queue Operation 0 0 1 1 0 1 0 1 None First opcode byte fetched from queue Queue was initialized Subsequent byte fetched from queue
DEBUG SUPPORT
The following signals are also used by emulators: A19-A0, AD15-AD0, {ADEN}, ALE, ARDY, BHE, BSIZE8, CAS1-CAS0, CLKOUT, {CLKSEL2-CLKSEL1}, HLDA, HOLD, LCS, MCS3-MCS0, NMI, {ONCE}, QS1-QS0, RAS1-RAS0, RD, RES, RESOUT, S2-S0, S6, SRDY, UCS, {UCSX8}, VCC, WHB, WLB, WR. See the Am186TMCC/CH/CU Microcontrollers User's Manual, order #21914, for more information. CHIP SELECTS LCS [RAS0] O Lower Memory Chip Select indicates to the system that a memory access is in progress to the lower memory block. The base address and size of the lower memory block are programmable up to 512 Kbyte. LCS can be configured for 8bit or 16-bit bus size. LCS is three-stated with a pullup resistor during bus-hold or reset conditions. Midrange Memory Chip Selects 3-0 indicate to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of the midrange memory block are programmable. The midrange chip selects can be configured for 8-bit or 16-bit bus size. The midrange chip selects are three-stated with pullup resistors during bus-hold or reset conditions. [MCS0] can be programmed as the chip select for the entire middle chip select address range. Unlike the UCS and LCS chip selects that operate relative to the earlier timing of the nonmultiplexed A address bus, the MCS outputs assert with the multiplexed AD address and data bus timing.
[MCS3]
[RAS1] PIO5 [CAS0] [CAS1] {UCSX8} PIO4
O
MCS2 MCS1 [MCS0]
Am186TMCC Communications Controller Data Sheet
19
Table 4. Signal Descriptions (Continued)
Signal Name [PCS7] [PCS6] [PCS5] Multiplexed Signal(s) PIO31 PIO32 PIO2 Type Description O Peripheral Chip Selects 7-0 indicate to the system that an access is in progress to the corresponding region of the peripheral address block (either I/O or memory address space). The base address of the peripheral address block is programmable. PCS7-PCS0 are three-stated with pullup resistors during bushold or reset conditions. Unlike the UCS and LCS chip selects that operate relative to the earlier timing of the nonmultiplexed A address bus, the PCS outputs assert with the multiplexed AD address and data bus timing.
[PCS4]
PIO3 {CLKSEL2} -- -- [PIO14] {USBSEL2} [PIO13] {USBSEL1} {ONCE} O
PCS3 PCS2 PCS1
PCS0
UCS
Upper Memory Chip Select indicates to the system that a memory access is in progress to the upper memory block. The base address and size of the upper memory block are programmable up to 512 Kbytes. UCS is three-stated with a weak pullup during bus-hold or reset conditions. The UCS can be configured for an 8-bit or 16-bit bus size out of reset. For additional information, see the {UCSX8} pin description in Table 31, "Reset Configuration Pins (Pinstraps)," on page A-10. After reset, UCS is active for the 64-Kbyte memory range from F0000h to FFFFFh, including the reset address of FFFF0h.
DRAM [CAS1] [CAS0] MCS1 MCS2 O Column Address Strobes 1-0: When either the upper or lower chip select regions are configured for DRAM, these pins provide the column address strobe signals to the DRAM. The CAS signals can be used to perform byte writes in a manner similar to WHB and WLB, respectively (i.e., [CAS0] corresponds to the low byte (WLB) and [CAS1] corresponds to the high byte (WHB)). Row Address Strobe 1: When the upper chip select region is configured to DRAM, this pin provides the row address strobe signal to the upper DRAM bank. Row Address Strobe 0: When the lower chip select region is configured to DRAM, this pin provides the row address strobe signal to the lower DRAM bank.
[RAS1] [RAS0]
[MCS3] PIO5 LCS
O O
20
Am186TMCC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name INTERRUPTS NMI -- STI Nonmaskable Interrupt indicates to the AM186CC controller that an interrupt request has occurred. The NMI signal is the highest priority hardware interrupt and cannot be masked. The controller always transfers program execution to the location specified by the nonmaskable interrupt vector in the controller's interrupt vector table when NMI is asserted. Although NMI is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. There is no bit associated with NMI in the interrupt in-service or interrupt request registers. This means that a new NMI request can interrupt an executing NMI interrupt service routine. As with all hardware interrupts, the interrupt flag (IF) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI interrupt service routine (for example, via the STI instruction), the fact that an NMI is currently in service does not have any effect on the priority resolution of maskable interrupt requests. For this reason, it is strongly advised that the interrupt service routine for NMI should not enable the maskable interrupts. An NMI transition from Low to High is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. To guarantee that the interrupt is recognized, the NMI pin must be asserted for at least one CLKOUT period. The board designer is responsible for properly terminating the NMI input. [INT8] [PWD] PIO6 PIO7 PIO19 -- STI Maskable Interrupt Requests 8-0 indicate to the AM186CC controller that an external interrupt request has occurred. If the individual pin is not masked, the controller transfers program execution to the location specified by the associated interrupt vector in the controller's interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. The interrupt polarity is programmable. To guarantee interrupt recognition for edge-triggered interrupts, the user should hold the interrupt source for a minimum of five system clocks. A second interrupt from the same source is not recognized until after an acknowledge of the first. The board designer is responsible for properly terminating the INT8-INT0 inputs. Also configurable as interrupts are PIO5, PIO15, PIO27, PIO29, PIO30, PIO33, PIO34, and PIO35. (See the Am186TMCC/CH/CU Microcontrollers User's Manual, order #21914 for more information.) Multiplexed Signal(s) Type Description
[INT7] [INT6] INT5-INT0
STI STI STI
Am186TMCC Communications Controller Data Sheet
21
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed Signal(s) (For multiplexed signals see Table 29, "PIOs Sorted by PIO Number," on page A-8 and Table 30, "PIOs Sorted by Signal Name," on page A-9.) Type Description
PROGRAMMABLE I/O (PIOS) PIO47-PIO0 B Shared Programmable I/O pins can be programmed with the following attributes: PIO function (enabled/disabled), direction (input/output), and weak pullup or pulldown. After a reset, the PIO pins default to various configurations. The column entitled "Pin Configuration Following System Reset" in Table 29 on page A-8 and Table 30 on page A-9 lists the defaults for the PIOs. Most of the PIO pins are configured as PIO inputs with pullup after reset. See Table 35 on page A-12 for detailed termination information for all pins. The system initialization code must reconfigure any PIO pins as required. PIO5, PIO15, PIO27, PIO29, PIO30, and PIO33-PIO35 are capable of generating an interrupt on the shared interrupt channel 14. The multiplexed signals ALE, ARDY, BHE, DEN, DT/R, PCS1-PCS0, SRDY, and WR default to non-PIO operation at reset. The following PIO signals are multiplexed with alternate signals that can be used by emulators: PIO8, PIO15, PIO33, PIO34, and PIO35. Consider any emulator requirements for the alternate signals before using these pins as PIOs. PROGRAMMABLE TIMERS [PWD] [INT8] PIO6 STI Pulse-Width Demodulator: If pulse-width demodulation is enabled, [PWD] processes a signal through the Schmitt trigger input. [PWD] is used internally to drive [TMRIN0] and [INT8], and [PWD] is inverted internally to drive [TMRIN1] and an additional internal interrupt. If interrupts are enabled and Timer 0 and Timer 1 are properly configured, the pulse width of the alternating [PWD] signal can be calculated by comparing the values in Timer 0 and Timer 1. In PWD mode, the signals [TMRIN0]/PIO27 and [TMRIN1]/PIO0 can be used as PIOs. If they are not used as PIOs they are ignored internally. The additional internal interrupt used in PWD mode uses the same interrupt channel as [INT7]. If [INT7] is to be used, it must be assigned to the shared interrupt channel. [TMRIN1] [TMRIN0] PIO0 PIO27 STI STI Timer Inputs 1-0 supply a clock or control signal to the internal AM186CC controller timers. After internally synchronizing a Low-to-High transition on [TMRIN1]-[TMRIN0], the microcontroller increments the timer. [TMRIN1]- [TMRIN0] must be tied High if not being used. When PIO is enabled for one or both, the pin is pulled High internally. [TMRIN1]-[TMRIN0] are driven internally by [INT8]/[PWD] when pulse-width demodulation functionality is enabled. The [TMRIN1]-[TMRIN0] pins can be used as PIOs when pulse-width demodulation is enabled. [TMROUT1] [TMROUT0] UART [RXD_U] DCE_RXD_D [PCM_RXD_D] PIO26 [DCE_TXD_D] [PCM_TXD_D] PIO20 STI Receive Data UART is the asynchronous serial receive data signal that supplies data from the asynchronous serial port to the microcontroller. Transmit Data UART is the asynchronous serial transmit data signal that supplies data to the asynchronous serial port from the microcontroller PIO1 PIO28 O O Timer Outputs 1-0 supply the system with either a single pulse or a continuous waveform with a programmable duty cycle. [TMROUT1]-[TMROUT0] are threestated during bus-hold or reset conditions.
ASYNCHRONOUS SERIAL PORTS (UART AND HIGH-SPEED UART)
[TXD_U]
O
22
Am186TMCC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name [CTS_U] Multiplexed Signal(s) [DCE_TCLK_D] [PCM_FSC_D] PIO24 Type Description STI Clear-To-Send UART provides the Clear-to-Send signal from the asynchronous serial port when hardware flow control is enabled for the port. The [CTS_U] signal gates the transmission of data from the serial port transmit shift register. When [CTS_U] is asserted, the transmitter begins transmission of a frame of data, if any is available. If [CTS_U] is deasserted, the transmitter holds the data in the serial port transmit shift register. The value of [CTS_U] is checked only at the beginning of the transmission of the frame. [CTS_U] and [RTR_U] form the hardware handshaking interface for the UART. Ready-To-Receive UART provides the Ready-to-Receive signal for the asynchronous serial port when hardware flow control is enabled for the port. The [RTR_U] signal is asserted when the associated serial port receive data register does not contain valid, unread data. [CTS_U] and [RTR_U] form the hardware handshaking interface for the UART. Receive Data High-Speed UART is the asynchronous serial receive data signal that supplies data from the high-speed serial port to the controller. Transmit Data High-Speed UART is the asynchronous serial transmit data signal that supplies data to the high-speed serial port from the microcontroller. Clear-To-Send High-Speed UART provides the Clear-to-Send signal from the high-speed asynchronous serial port when hardware flow control is enabled for the port. The [CTS_HU] signal gates the transmission of data from the serial port transmit shift register. When [CTS_HU] is asserted, the transmitter begins transmission of a frame of data, if any is available. If [CTS_HU] is deasserted, the transmitter holds the data in the serial port transmit shift register. The value of [CTS_HU] is checked only at the beginning of the transmission of the frame. [CTS_HU] and [RTR_HU] form the hardware handshaking interface for the HighSpeed UART. Ready-To-Receive High-Speed UART provides the Ready-to-Receive signal to the high-speed asynchronous serial port when hardware flow control is enabled for the port. The [RTR_HU] signal is asserted when the associated serial port receive data register does not contain valid, unread data. [CTS_HU] and [RTR_HU] form the hardware handshaking interface for the High-Speed UART. Serial Clock provides the clock for the synchronous serial interface to allow synchronous transfers between the AM186CC controller and a slave device. Serial Data is used to transmit and receive data between the AM186CC controller and a slave device on the synchronous serial interface. Serial Data Enable enables data transfers on the synchronous serial interface.
[RTR_U]
DCE_RCLK_D [PCM_CLK_D] PIO25
O
High-Speed UART [RXD_HU] TXD_HU [CTS_HU] PIO16 -- [DCE_CTS_D] [PCM_TSC_D] PIO46 STI O STI
[RTR_HU]
[DCE_RTR_D] PIO47
O
SYNCHRONOUS SERIAL INTERFACE (SSI) [SCLK] [SDATA] [SDEN] PIO11 PIO12 PIO10 O B O
HIGH-LEVEL DATA LINK CONTROL SYNCHRONOUS COMMUNICATION INTERFACES HDLC Channel A (DCE) DCE_RXD_A DCE_TXD_A DCE_RCLK_A [GCI_DD_A] [PCM_RXD_A] [GCI_DU_A] [PCM_TXD_A] [GCI_DCL_A] [PCM_CLK_A] STI DCE Receive Data Channel A is the serial data input pin for the channel A DCE interface.
OD-O DCE Transmit Data Channel A is the serial data output pin for the channel A DCE interface. STI DCE Receive Clock Channel A provides the receive clock to the channel A DCE interface. If the same clock is to be used for both transmit and receive, then this pin should be tied to the DCE_TCLK_A pin externally. The DCE function is the default at reset, so the board designer is responsible for properly terminating the DCE_RCLK_A input.
Am186TMCC Communications Controller Data Sheet
23
Table 4. Signal Descriptions (Continued)
Signal Name DCE_TCLK_A Multiplexed Signal(s) [GCI_FSC_A] [PCM_FSC_A] Type Description STI DCE Transmit Clock Channel A provides the transmit clock to the channel A DCE interface. If the same clock is to be used for both transmit and receive, then this pin should be tied to the DCE_RCLK_A pin externally. The DCE function is the default at reset, so the board designer is responsible for properly terminating the DCE_TCLK_A input. [DCE_CTS_A] [PCM_TSC_A] PIO17 PIO18 STI DCE Clear To Send Channel A indicates to the channel A DCE interface that an external serial interface is ready to receive data. [DCE_CTS_A] and [DCE_RTR_A] provide the handshaking for DCE Channel A. DCE Ready to Receive Channel A indicates to an external serial interface that the internal channel A DCE interface is ready to accept data. [DCE_CTS_A] and [DCE_RTR_A] provide the handshaking for the channel A DCE interface. DCE Receive Data Channel B is the serial data input pin for the channel B DCE interface. DCE Transmit Data Channel B is the serial data output pin for the channel B DCE interface. DCE Receive Clock Channel B provides the receive clock to the channel B DCE interface. If the same clock is to be used for both transmit and receive, this pin should be tied to the [DCE_TCLK_B] pin externally. DCE Transmit Clock Channel B provides the transmit clock to the channel B DCE interface. If the same clock is to be used for both transmit and receive, this pin should be tied to the [DCE_RCLK_B] pin externally. DCE Clear To Send Channel B indicates to the channel B DCE interface that an external serial interface is ready to receive data. [DCE_CTS_B] and [DCE_RTR_B] provide the handshaking for the channel B DCE interface. DCE Ready to Receive Channel B indicates to an external serial interface that the internal channel B DCE interface is ready to accept data. [DCE_CTS_B] and [DCE_RTR_B] provide the handshaking for the channel B DCE interface. DCE Receive Data Channel C is the serial data input pin for the channel C DCE interface. DCE Transmit Data Channel C is the serial data output pin for the channel C DCE interface. DCE Receive Clock Channel C provides the receive clock to the channel C DCE interface. If the same clock is to be used for both transmit and receive, this pin should be tied to the [DCE_TCLK_C] pin externally. DCE Transmit Clock Channel C provides the transmit clock to the channel C DCE interface. If the same clock is to be used for both transmit and receive, this pin should be tied to the [DCE_RCLK_C] pin externally. DCE Clear To Send Channel C indicates to the channel C DCE interface that an external serial interface is ready to receive data. [DCE_CTS_C] and [DCE_RTR_C] provide the handshaking for the channel C DCE interface. DCE Ready to Receive Channel C indicates to an external serial interface that the internal channel C DCE is ready to accept data. [DCE_CTS_C] and [DCE_RTR_C] provide the handshaking for the channel C DCE interface. DCE Receive Data Channel D is the serial data input pin for the channel D DCE interface.
[DCE_RTR_A]
O
HDLC Channel B (DCE) [DCE_RXD_B] [DCE_TXD_B] [PCM_RXD_B] PIO36 [PCM_TXD_B] PIO37 STI
OD-O
[DCE_RCLK_B] [PCM_CLK_B] PIO40 [DCE_TCLK_B] [PCM_FSC_B] PIO41 [PCM_TSC_B] PIO38 PIO39
STI
STI
[DCE_CTS_B]
STI
[DCE_RTR_B]
O
HDLC Channel C (DCE) [DCE_RXD_C] [DCE_TXD_C] [PCM_RXD_C] PIO42 [PCM_TXD_C] PIO43 STI
OD-O
[DCE_RCLK_C] [PCM_CLK_C] PIO22 [DCE_TCLK_C] [PCM_FSC_C] PIO23 [DCE_CTS_C] [PCM_TSC_C] PIO44 PIO45
STI
STI
STI
[DCE_RTR_C]
O
HDLC Channel D (DCE) DCE_RXD_D [RXD_U] (UART) [PCM_RXD_D] PIO26 STI
24
Am186TMCC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name [DCE_TXD_D] Multiplexed Signal(s) [TXD_U] (UART) [PCM_TXD_D] PIO20 [RTR_U] (UART) [PCM_CLK_D] PIO25 Type Description
OD-O
DCE Transmit Data Channel D is the serial data output pin for the channel D DCE interface. DCE Receive Clock Channel D provides the receive clock to the channel D DCE interface. If the same clock is to be used for both transmit and receive, then this pin should be tied to the [DCE_TCLK_D] pin externally. DCE Transmit Clock Channel D provides the transmit clock to the channel D DCE interface. If the same clock is to be used for both transmit and receive, then this pin should be tied to the DCE_RCLK_D pin externally. DCE Clear To Send Channel D indicates to the channel D DCE interface that an external serial interface is ready to receive data. [DCE_CTS_D] and [DCE_RTR_D] provide the handshaking for DCE Channel D. DCE Ready To Receive Channel D indicates to an external serial interface that the internal channel D DCE interface is ready to accept data. [DCE_CTS_D] and [DCE_RTR_D] provide the handshaking for the channel D DCE interface. PCM Receive Data Channel A is the serial data input pin for the channel A PCM Highway interface. PCM Transmit Data Channel A is the serial data output pin for the channel A PCM Highway interface. PCM Clock is the single transmit and receive data clock pin for the channel A PCM Highway interface. PCM Frame Synchronization Clock provides the Frame Synchronization Clock input (usually 8 kHz) for the channel A PCM Highway interface. PCM Time Slot Control A enables an external buffer device when channel A PCM Highway data is present on the [PCM_TXD_A] output pin in PCM Highway mode. PCM Receive Data Channel B is the serial data input pin for the channel B PCM Highway interface. PCM Transmit Data Channel B is the serial data output pin for the channel B PCM Highway interface. PCM Clock is the single transmit and receive data clock pin for the channel B PCM Highway interface. PCM Frame Synchronization Clock provides the Frame Synchronization Clock input (usually 8 kHz) for the channel B PCM Highway interface. PCM Time Slot Control B enables an external buffer device when channel B PCM Highway data is present on the [PCM_TXD_B] output pin in PCM Highway mode. PCM Receive Data Channel C is the serial data input pin for the channel C PCM Highway interface. PCM Transmit Data Channel C is the serial data output pin for the channel C PCM Highway interface. PCM Clock: For PCM Highway operation, [PCM_CLK_C] is the single transmit and receive data clock input pin for the channel C PCM Highway interface. [PCM_CLK_C] becomes a clock source output when the GCI to PCM Highway clock and frame synchronization conversion are enabled.
DCE_RCLK_D
STI
[DCE_TCLK_D] [CTS_U] (UART) [PCM_FSC_D] PIO24 [DCE_CTS_D] [CTS_HU] (HighSpeed UART) [PCM_TSC_D] PIO46 [RTR_HU] (HighSpeed UART) PIO47 DCE_RXD_A [GCI_DD_A] DCE_TXD_A [GCI_DU_A] DCE_RCLK_A [GCI_DCL_A] DCE_TCLK_A [GCI_FSC_A] [DCE_CTS_A] PIO17
STI
STI
[DCE_RTR_D]
O
HDLC Channel A (PCM) [PCM_RXD_A] [PCM_TXD_A] [PCM_CLK_A] [PCM_FSC_A] [PCM_TSC_A] STI
O-LSOD
STI STI OD
HDLC Channel B (PCM) [PCM_RXD_B] [PCM_TXD_B] [PCM_CLK_B] [PCM_FSC_B] [PCM_TSC_B] [DCE_RXD_B] PIO36 [DCE_TXD_B] PIO37 [DCE_RCLK_B] PIO40 [DCE_TCLK_B] PIO41 [DCE_CTS_B] PIO38 STI
O-LSOD
STI STI OD
HDLC Channel C (PCM) [PCM_RXD_C] [PCM_TXD_C] [PCM_CLK_C] [DCE_RXD_C] PIO42 [DCE_TXD_C] PIO43 [DCE_RCLK_C] PIO22 STI
O-LSOD
STIO
Am186TMCC Communications Controller Data Sheet
25
Table 4. Signal Descriptions (Continued)
Signal Name [PCM_FSC_C] Multiplexed Signal(s) [DCE_TCLK_C] PIO23 Type Description B PCM Frame Synchronization Clock: For PCM Highway operation, [PCM_FSC_C] provides the Frame Synchronization Clock input (usually 8 kHz) for the channel C PCM Highway interface. [PCM_FSC_C] becomes a frame synchronization source output when the GCI to PCM Highway clock and frame synchronization conversion are enabled. PCM Time Slot Control C enables an external buffer device when channel C PCM Highway data is present on the [PCM_TXD_C] output pin in PCM Highway mode. PCM Receive Data Channel D is the serial data input pin for the channel D PCM Highway interface. PCM Transmit Data Channel D is the serial data output pin for the channel D PCM Highway interface. PCM Clock is the single transmit and receive data clock pin for the channel D PCM Highway interface. PCM Frame Synchronization Clock provides the Frame Synchronization Clock input (usually 8 kHz) for the channel D PCM Highway interface. PCM Time Slot Control D enables an external buffer device when channel D PCM Highway data is present on the [PCM_TXD_D] output pin in PCM Highway mode.
[PCM_TSC_C]
[DCE_CTS_C] PIO44
OD
HDLC Channel D (PCM) [PCM_RXD_D] [RXD_U] (UART) DCE_RXD_D PIO26 [TXD_U] (UART) [DCE_TXD_D] PIO20 [RTR_U] (UART) DCE_RCLK_D PIO25 [CTS_U] (UART) [DCE_TCLK_D] PIO24 [CTS_HU] (HighSpeed UART) [DCE_CTS_D] PIO46 DCE_RXD_A [PCM_RXD_A] DCE_TXD_A [PCM_TXD_A] DCE_RCLK_A [PCM_CLK_A] DCE_TCLK_A [PCM_FSC_A] USBD- USBD+ STI
[PCM_TXD_D]
O-LSOD
[PCM_CLK_D]
STI
[PCM_FSC_D]
STI
[PCM_TSC_D]
OD
HDLC Channel A (GCI) [GCI_DD_A] [GCI_DU_A] [GCI_DCL_A] [GCI_FSC_A] BOD BOD STI STI GCI Data Downstream is the serial data input pin for the channel A GCI interface. GCI Data Upstream is the serial data output pin for the channel A GCI interface. GCI Data Clock is the single transmit and receive channel A GCI data clock input generated by an upstream device. The data clock frequency must be twice the data rate. GCI Frame Synchronization Clock provides the 8-kHz Frame Synchronization Clock input for the channel A GCI interface generated by an upstream device. USB External Transceiver Gated Differential Plus and USB External Transceiver Gated Differential Minus are inputs from the external USB transceiver used to detect single-ended zero and error conditions. The signals have the following meanings: USB External Transceiver Signals UDPLS 0 0 1 1 UDMNS 0 1 0 1 Status Single-Ended Zero (SE0) Full speed Reserved Error
UNIVERSAL SERIAL BUS [UDMNS] [UDPLS] STI STI
USBD+ USBD-
[UDPLS] [UDMNS]
B B
USB Differential Plus and USB Differential Minus form the bidirectional electrical data interface for the USB port. The pins form a differential pair that can be connected to a physical USB connector without an external transceiver.
26
Am186TMCC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Signal Name [USBSCI] Multiplexed Signal(s) [UCLK] [USBSOF] PIO21 [UCLK] [USBSCI] PIO21 RSVD_102 RSVD_101 RSVD_103 Type Description STI USB Sample Clock Input is used to synchronize an external clock to the internal USB peripheral controller for isochronous transfers. USB Start of Frame is a 1-kHz frame pulse used to synchronize USB isochronous transfers to an external device on a frame-by-frame basis. USB External Transceiver Differential Minus is an output that drives the external transceiver differential driver minus input. USB External Transceiver Differential Plus is an output that drives the external transceiver differential driver plus input. USB External Transceiver Transmit Output Enable is an output that enables the external transceiver. UXVOE signals the external transceiver that USB data is being output by the AM186CC USB controller. When Low, this pin enables the transceiver output; when High, this pin enables the receiver. USB External Transceiver Differential Receiver is a data input received from the external transceiver differential receiver.
[USBSOF]
O
UTXDMNS UTXDPLS UXVOE
O O O
UXVRCV
RSVD_104
STI
Am186TMCC Communications Controller Data Sheet
27
ARCHITECTURAL OVERVIEW
The architectural goal of the AM186CC microcontroller is to provide comprehensive communications features on a processor r unning the widely known x86 instr uction set. The AM186CC microcontroller combines four HDLC channels, a USB peripheral controller, and general communications peripherals with the Am186 microcontroller. This highly integrated microcontroller provides system cost and performance advantages for a wide range of communications applications. Figure 1 is a block diagram of the AM186CC microcontroller, followed by sections providing an overview of the features of the AM186CC microcontroller.
Serial Communications Peripherals
Am186 CPU Chip Selects (14) PIOs (48) Watchdog Timer Interrupt Controller (17 Ext. Sources) UART High-Speed UART with Autobaud USB Synchronous Serial Interface (SSI)
Physical Interface Glueless Interface to RAM/ROM DRAM Controller Timers (3) GeneralPurpose DMA (4) SmartDMA Channels (8) HDLC HDLC TSA TSA Muxing HDLC HDLC TSA GCI (IOM-2) TSA Raw DCE PCM Highway
Memory Peripherals
System Peripherals
Figure 1.
AM186CC Controller Block Diagram
Detailed Description
n Universal Serial Bus (USB) peripheral controller works with a wide variety of USB devices - Implements high-speed 12-Mbit/s device function - Allows an unlimited number of device descriptors - Supports a total of six endpoints: one control endpoint; one interrupt endpoint; four data endpoints that can be either bulk or isochronous, IN or OUT - Two data endpoints have 16-byte FIFOs; two data endpoints have 64-byte FIFOs - Fully integrated differential driver directly supports the USB interface (D+, D-) - Specialized hardware supports adaptive isochronous data streams - General-purpose DMA and SmartDMATM channels supported n Four independent High-level Data Link Control (HDLC) channels support a wide range of external interfaces - External interface connection for HDLCs can be PCM Highway, GCI, or raw DCE - Data rate of up to 10 Mbit/s - Receive and transmit FIFOs - Support for HDLC, Synchronous Data Link Control (SDLC), Line Access Procedure Balanced (LAP-B), Line Access Procedure D (LAP-D), Point-to-Point Protocol (PPP), and v.120 (support of v.110 in transparent mode) - Two dedicated buffer descriptor ring SmartDMA channels per HDLC - One independent time-slot assigner per HDLC - Clear to Send/Ready to Receive (CTS/RTR) hardware handshaking and auto-enable operation - Collision detection for multidrop applications - Transparency mode - Address comparison on receive - Flag or mark idle operation
28
Am186TMCC Communications Controller Data Sheet
n Four independent Time Slot Assigners (TSAs) provide flexible time slot allocation - Allows isolation of Time Division Multiplexed (TDM) time slot of choice from a variety of TDM carriers - Up to 4096 sequential bits isolated - TDM bus can have up to 512 8-bit time slots - Start bit and stop bit times identify isolated portion of TDM frame - 12-bit counters define the start/stop bit times as the number of bits after frame synchronization - Entire frame down to 1 bit per frame can be isolated n 12 Direct Memory Access (DMA) channels - Eight buffer descriptor ring SmartDMA channels for the four HDLC channels and, optionally, USB bulk and isochronous endpoints - Four general-purpose DMAs support the two integrated asynchronous serial ports and/or USB endpoints. Two DMA channels have external DMA request inputs n High-speed asynchronous serial interface provides enhanced UART functions - Capable of sustained operation at 460 Kbaud - 7-, 8-, or 9-bit data transfers - FIFOs to support high-speed operation - DMA support available - Automatic baud rate detection that allows emulation of a Hayes AT-compatible modem - Independent baud generator with clock input source programmable to use CPU or external clock input pin n Asynchronous serial interface (UART) - 7-, 8-, or 9-bit data transfers - DMA support available
- Independent baud generator with clock input source programmable to use CPU or external clock input pin n General Circuit Interface (GCI) provides IOM-2 Terminal Mode connection - Glueless connection between the AM186CC microcontroller and GCI-based ISDN transceiver devices, such as the Am79C30/Am79C32 Four-pin GCI connection Terminal mode operation Slave mode with pin reversal Telecom IC (TIC) bus support for D channel arbitration and collision detection - Support for one Monitor and two Command/ Indicate channels - Clock and Frame Sync conversion for PCM Highway coder-decoders (codecs) n Synchronous Serial Interface (SSI) provides half-duplex, bidirectional interface to highspeed peripherals - Useful with many telecommunication interface peripherals such as codecs, line interface units, and tranceivers - Selectable device-select polarity - Selectable bit shift order on transmit and receive - Glueless connection to AMD Subscriber Line Audio Processing Circuit (SLACTM) devices n Clocking options offer high flexibility - Separate crystal oscillator inputs for system and USB clock sources - CPU can run in 1x, 2x, or 4x mode - USB can run in 2x or 4x mode - USB can run from system clock if running at 48 MHz, allowing entire system to run from one 12-MHz or 24-MHz crystal and adding the 16-bit offset value to yield a 20-bit physical address (see Figure 2 on page 30). This allows for a 1-Mbyte physical address size. All instructions that address operands in memory must specify the segment value and the 16-bit offset value. For speed and compact instruction encoding, the segment register used for physical address generation is implied by the addressing mode used (see Table 5 on page 30). - - - -
Am186 Embedded CPU
All members of the Am186 family, including the AM186CC microcontroller, are compatible with the original industry-standard 186 parts, and build on the same core set of 186 registers, I/O space, address generation, instruction set, segments, data types, and addressing modes.
Memory Organization
Memory is organized in sets of segments. Each segment is a linear contiguous sequence of 64K (216) 8-bit bytes. Memor y is addressed using a twocomponent address consisting of a 16-bit segment value and a 16-bit offset. The 16-bit segment values are contained in one of four internal segment registers (CS, DS, SS, or ES). The physical address is calculated by shifting the segment value left by 4 bits
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit ports. Separate instructions (IN, INS and OUT, OUTS) address the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX register. Eight-bit port addresses are zeroextended such that A15-A8 are Low.
Am186TMCC Communications Controller Data Sheet
29
Shift Left 4 Bits
15 1 15 0 0 2 2 A
0 4 0 2 Offset Segment Base Logical Address
19 1 2 15 0 19 1 2 A 6 0 0 2 A 4
0 0 0 2 0 2 Physical Address
To Memory
Figure 2.
Two-Component Address Example
Table 5. Segment Register Selection Rules
Memory Reference Needed Instructions Local Data Stack External Data (Global) Segment Register Used Implicit Segment Selection Rule Code (CS) Instructions (including immediate data) Data (DS) All data references All stack pushes and pops; Stack (SS) any memory references that use the BP register Extra (ES) All string instruction references that use the DI register as an index
Serial Communications Support
The AM186CC microcontroller supports eight serial interfaces. This includes four HDLC channels, a USB peripheral controller, two UARTs, and a synchronous serial interface. Universal Serial Bus The AM186CC microcontroller includes a highly flexible integrated USB peripheral controller that lets designers implement a variety of microcontroller-based USB peripheral devices for telephony, audio, and other high-end applications. This integrated USB peripheral controller can provide a significant system-cost reduction compared to other platforms that require a separate USB controller. The AM186CC microcontroller can be used in selfpowered USB peripherals that use the full-speed signalling rate of 12 Mbit/s. The USB low-speed rate (1.5 Mbit/s) is not supported. An integrated USB transceiver is provided to minimize system device count and cost, but an external transceiver can be used instead, if necessary. The USB controller does not support USB host or hub functions. However, the AM186CC microcontroller can be used to implement USB peripheral functions in a device that also contains separate USB hub circuitry. In addition, the AM186CC USB controller supports the following: n An unlimited number of device descriptors n A total of 6 endpoints: 1 control endpoint, 1 interrupt endpoint, and 4 data endpoints that can be configured as control, interrupt, bulk, or isochronous. The interrupt, bulk, and isochronous endpoints can be configured for the IN or OUT direction. n Two data endpoints have 16-byte FIFOs; two data endpoints have 64-byte FIFOs n Fully integrated differential driver, which supports the USB interface directly n Specialized hardware, which supports adaptive isochronous data streams and automatically synchronizes with HDLC data streams n General-purpose DMA and SmartDMA channels
30
Am186TMCC Communications Controller Data Sheet
Four HDLC Channels and Four TSAs The AM186CC microcontroller provides four HDLC channels that support the HDLC, SDLC, LAP-B, LAP-D, PPP, and v.120 protocols. The HDLC channels can also be used in transparent mode to support v.110. Each HDLC channel can connect to an external serial interface directly (nonmultiplexed mode), or can pass through a TSA (multiplexed mode). The flexible interface multiplexing arrangement allows each HDLC channel to have its own external raw DCE or PCM highway interface, share the GCI interface with up to two other channels, share a common PCM highway or other time TDM bus with three or more channels, or work in some combination. Each HDLC channel's independent TSA allows it to extract a subset of data from a TDM bus. The entire frame, or as little as 1 bit per frame, can be extracted. Twelve-bit counters define the start/stop bit times as the number of bits after frame synchronization. The time slot can be an arbitrary number of bits up to 4096 bits. Start bit and stop bit times identify the isolated portion of the TDM frame. Support of less than eight bits per time slot, or bit slotting, allows isolation of from one to eight bits in a single time slot, providing a convenient way to work with D-channel data. Each TDM bus can have up to 512 8-bit time slots. Support of these features allows interoperation with PCM highway, E1, IOM-2, T1, and other TDM buses. The HDLC channels have features that make the AM186CC microcontroller an attractive device for use where general HDLC capability is required. These features include CTS/RTR hardware handshaking and auto-enable operation, collision detection for multidrop applications, transparency mode, address comparison on receive, flag or mark idle operation, two dedicated buffer descriptor ring SmartDMA channels per HDLC, transmit and receive FIFOs, and full-duplex data transfer. Each TSA channel can support a burst data rate to/from the HDLC of up to 10 Mbit/s in both raw DCE and PCM Highway modes, and up to 768 Kbit/s in GCI mode. Total system data throughput is highly dependent on the amount of per-packet and per-byte CPU processing, the rate at which packets are being sent, and other CPU activity. When combined with the TSAs, the HDLC channels can be used in a wide variety of applications such as ISDN basic rate interface (BRI) and primary rate interface (PRI) B and D channels, PCM highway, X.25, Frame Relay, and other proprietary Wide Area Network (WAN) connections. General Circuit Interface The General Circuit Interface (GCI) is an interface specification developed jointly by Alcatel, Italtel, GPT, and Siemens. This specification defines an industry-
standard ser ial bus for interconnecting telecommunications integrated circuits. The standard covers linecard, NT1, and terminal architectures for ISDN applications. The AM186CC microcontroller supports the terminal version of GCI. The AM186CC GCI interface provides a glueless connection between the AM186CC microcontroller and GCI/IOM-2 based ISDN transceiver devices, such as the AMD Am79C30 or Am79C32. The AM186CC microcontroller GCI interface provides a 4-pin connection to the transceiver device. The AM186CC microcontroller also allows conversion of the GCI clock and frame synchronization into a format usable by PCM codecs, allowing PCM codecs to be used directly with GCI/IOM-2 transceivers. Additional GCI features include slave mode with pin reversal, Terminal Interchip Communication (TIC) bus support for D channel arbitration and collision detection, and support for one Monitor and two Command/Indicate channels. Eight SmartDMATM Channels The AM186CC microcontroller provides a total of 12 DMA channels. Eight of these channels are SmartDMA channels, which provide a method for transmission and reception of data across multiple memory buffers and a sophisticated buffer-chaining mechanism. These channels are always used in pairs: transmitter and receiver. The transmit channels can only transfer data from memory to a peripheral; the receive channels can only transfer data from a peripheral to memory. Four of the channels (two pairs) are dedicated for use with two of the on-board HDLC channels. The remaining four SmartDMA channels (two pairs) can support either the third or fourth HDLC channel or USB endpoints A, B, C, or D. In addition to the eight SmartDMA channels, the AM186CC microcontroller provides four generalpurpose DMA channels. For more information about the four general-purpose DMA channels, refer to "Four General-Purpose DMA Channels" on page 32. Two Asynchronous Serial Ports The AM186CC microcontroller has two asynchronous serial ports (a UART and a High-Speed UART) that provide full-duplex, bidirectional data transfer at speeds of up to 115.2 Kbit/s or up to 460 Kbit/s, respectively. The High-Speed UART has 16-byte transmit and 32-byte receive FIFOs, special-character matching, and automatic baud-rate detection, which is suitable for implementation of a Hayes-compatible modem interface to a host PC. A lower speed UART is also available that is typically used for a low baud-rate system configuration port or debug port. Each of these UARTs can derive its baud rate from the system clock or from a separate baud-rate generator clock input. Both UARTs support 7-, 8-, or 9-bit data transfers;
Am186TMCC Communications Controller Data Sheet
31
address bit generation and detection in 7- or 8-bit frames; one or two stop bits; even, odd, or not parity; break generation and detection; hardware flow control; and DMA to and/or from the serial ports using the general-purpose DMA channels. Synchronous Serial Port The AM186CC microcontroller includes one SSI, which provides a half-duplex, bidirectional, communications interface between the AM186CC microcontroller and other system components. This interface is typically used by the AM186CC microcontroller to monitor the status of other system devices and/or to configure these devices under software control. In a communications application, these devices could be system components such as audio codecs, line interface units, and transceivers. The SSI supports data transfer speeds of up to 25 Mbit/s with a 50-MHz system clock. The AM186CC SSI port operates as an interface master, with the other attached devices acting as slave d ev i c e s . U s i n g t h i s p r o t o c o l , t h e A m 1 8 6 C C microcontroller sends a command byte to the attached device, and then follows that with either a read or write of a byte of data. The SSI port consists of three I/O pins: an enable (SDEN), a clock (SCLK), and a bidirectional data pin (SDATA). SDEN can be used directly as an enable for a single attached device. When more than one device requires control via the SSI, PIOs can be used to provide enable pins for those devices. The AM186CC SSI is, in general, software compatible with software written for the Am186EM SSI. (Additional features have been added to the AM186CC SSI implementation.) In addition, the AM186CC microcontroller features the additional capability of selecting the polarity of the SCLK and SDEN pins, as well as the shift order of bits on the SDATA pin (leastsignificant-bit first versus most-significant-bit first). The AM186CC SSI port also offers a programmable clock divisor (dividing the clock from 2 to 256 in power of 2 increments), a bidirectional transmit/receive shift register, and direct connection to AMD SLAC devices.
The AM186CC interrupt controller suppor ts 36 maskable interrupt sources through the use of 15 channels. Because of this, most channels support multiple interrupt sources. These channels are programmable to support the external interrupt pins and/ or various peripheral devices that can be configured to generate interrupts. The 36 maskable interrupt sources include 19 internal sources and 17 external sources. Four General-Purpose DMA Channels The AM186CC microcontroller provides a total of 12 DMA channels. Four of the channels are general purpose and can be used for data transfer between memory and I/O spaces (i.e., memory-to-I/O or I/O-tomemory) or within the same space (i.e., memory-tomemory or I/O-to-I/O). In addition, the AM186CC microcontroller suppor ts data transfer between peripherals and memory or I/O. On-chip peripherals that support general-purpose DMA are Timer 2, the two asynchronous serial ports (UART and High-Speed UART), and the USB controller. External peripherals support DMA transfers through the external DMA request pins. Each general-purpose channel can accept synchronized DMA requests from one of four sources: the DMA request pins (DRQ1-DRQ0), Timer 2, the UARTs, or the USB controller. In addition to the four general-pur pose channels, the AM186CC microcontroller provides eight SmartDMA channels. For more information about the eight SmartDMA channels, refer to "Eight SmartDMATM Channels" on page 31. 48 Programmable I/O Signals The AM186CC microcontroller provides 48 userprogrammable input/output signals (PIOs). Each of these signals shares a pin with at least one alternate function. If an application does not need the alternate func tion, the as soc iate d PIO c an be us ed by programming the PIO registers. If a pin is enabled to function as a PIO signal, the alternate function is disabled and does not affect the pin. A PIO signal can be configured to operate as an input or output, with or without internal pullup or pulldown resistors (pullup or pulldown depends on the pin configuration and is not user-configurable), or as an open-drain output. Additionally, eight PIOs can be configured as external interrupt sources. Three Programmable Timers There are three 16-bit programmable timers in the AM186CC microcontroller. Timers 0 and 1 are highly versatile and are each connected to two external pins (each one has an input and an output). These two timers can be used to count or time external events that drive the timer input pins. Timers 0 and 1 can also be used to generate nonrepetitive or variable-duty-cycle waveforms on the timer output pins.
System Peripherals
Interrupt Controller The AM186CC microcontroller features an interrupt controller, which arranges the 36 maskable interrupt requests by priority and presents them one at a time to the CPU. In addition to interrupts managed by the interrupt controller, the AM186CC microcontroller supports eight nonmaskable interrupts--an external or internal nonmaskable interrupt (NMI), a trace interrupt, and software interrupts and exceptions.
32
Am186TMCC Communications Controller Data Sheet
Timer 2 is not connected to any external pins. It can be used by software to generate interrupts, or it can be polled for real-time coding and time-delay applications. Timer 2 can also be used as a prescaler to Timer 0 and Timer 1, or as a DMA request source. The source clock for Timer 2 is one-fourth of the system clock frequency. The source clock for Timers 0 and 1 can be configured to be one-fourth of the system clock, or they can be driven from their respective timer input pins. When driven from a timer input pin, the timer is counting the "event" of an input transition. The AM186CC microcontroller also provides a pulse width demodulation (PWD) option so that a toggling input signal's Low state and High state durations can be measured. Hardware Watchdog Timer The AM186CC microcontroller provides a full-featured watchdog timer, which includes the ability to generate Non-Maskable Interrupts (NMIs), microcontroller resets, and system resets when the timeout value is reached. The timeout value is programmable and ranges from 210 to 226 processor clocks. The watchdog timer is used to regain control when a system has failed due to a software error or to failure of an external device to respond in the expected way. Software errors can sometimes be resolved by recapturing control of the execution sequence via a watchdog-timer-generated NMI. When an external device fails to respond, or responds incorrectly, it may be necessary to reset the controller or the entire system, including external devices. The AM186CC watchdog timer provides the flexibility to support both NMI and reset generation.
CH/CU Microcontrollers Register Set Manual (order #21916).
Accesses to the PCB should be performed by direct processor actions. The use of DMA to write or read from the PCB results in unpredictable behavior, except where explicit exception is made to suppor t a peripheral function, such as the High-Speed UART transmit and receive data registers. The 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t1 clock phase. The AM186CC microcontroller continues to provide the multiplexed AD bus and, in addition, provide a nonmultiplexed address (A) bus. The A bus provides an address to the system for the complete bus cycle (t1- t4). During refresh cycles, the AD bus is driven during the t1 phase and the values are unknown during the t2, t3, and t4 phases. The value driven on the A bus is undefined during a refresh cycle. The nonmultiplexed address bus (A19-A0) is valid onehalf CLKOUT cycle in advance of the address on the AD bus. When used with the modified UCS and LCS outputs and the byte write enable signals, the A19-A0 bus provides a seamless interface to SRAM, DRAM, and Flash/EPROM memory systems. For systems where power consumption is a concern, it is possible to disable the address from being driven on the AD bus on the AM186CC microcontroller during the normal address portion of the bus cycle for accesses to upper (UCS) and/or lower (LCS) address spaces. In this mode, the affected bus is placed in a highimpedance state during the address portion of the bus cycle. This feature is enabled through the DA bits in the Upper Memor y Chip Select (UMCS) and Lower Memory Chip Select (LMCS) registers. When address disable is in effect, the number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, thus decreasing power consumption, reducing processor switching noise, and preventing bus contention with memory devices and peripherals when operating at high clock rates. If the ADEN pin is asserted during processor reset, the value of the DA bits in the UMCS and LMCS registers is ignored and the address is driven on the AD bus for all accesses, thus preserving the industry-standard 80C186 and 80C188 microcontrollers' multiplexed address bus and providing support for existing emulation tools. For r e g i s t e r s, r e f e r t o t h e A m 1 8 6 TM C C /C H / C U Microcontrollers Register Set Manual (order #21916). Figure 3 on page 35 shows the affected signals during a normal read or write operation. The address and data are multiplexed onto the AD bus.
Memory and Peripheral Interface
System Interfaces The AM186CC bus interface controls all accesses to the peripheral control block (PCB), memory-mapped and I/O-mapped external peripherals, and memory devices. Internal peripherals are accessed by the bus interface through the PCB. The AM186CC bus interface features programmable bus sizing; individually selectable chip selects for the upper (UCS) memory space, lower (LCS) memory space, all non-UCS, non-LCS and I/O memory spaces; separate byte-write enables; and boot option from an 8or 16-bit device. The integrated peripherals are controlled by 16-bit read/write registers. The peripheral registers are contained within an internal 1-Kbyte control block. At reset, the base of the PCB is set to FC00h in I/O space. The registers are physically located in the peripheral devices they control, but they are addressed as a single 1-Kbyte block. For registers, refer to the Am186TMCC/
Am186TMCC Communications Controller Data Sheet
33
Figure 4 on page 36 shows a bus cycle when address bus disable is in effect, which causes the AD bus to operate in a nonmultiplexed data-only mode. The A bus has the address during a read or write operation.
Bus Interface Unit
The bus interface unit controls all accesses to external peripherals and memory devices. External accesses include those to memory devices, as well as those to memorymapped and I/O-mapped peripherals and the peripheral control block. The AM186CC microcontroller provides an enhanced bus interface unit with the following features: n Nonmultiplexed address bus n Separate byte write enables for high and low bytes n Output enable The standard 80C186/80C188 multiplexed address and data bus requires system interface logic and an external address latch. On the AM186CC microcontroller, byte write enables and a nonmultiplexed address bus can reduce design costs by eliminating this external logic.
Mode DRAM, Asymmetrical DRAM, and 8-bit wide DRAM are not suppor ted. The AM186CC microcontroller includes a glueless DRAM interface providing zero-wait state operation at up to 50 MHz with 40-ns DRAM. This allows designs requiring larger amounts of memory to save system cost over SRAM designs by taking advantage of low DRAM memory costs. The DRAM interface uses various chip select pins to implement the RAS/CAS interface required by DRAMs. The AM186CC DRAM controller drives the RAS/CAS interface appropriately during both normal memory accesses and during refresh. All signals required are generated by the AM186CC microcontroller and no external logic is required. The DRAM multiplexed address pins are connected to the AM186CC microcontroller's odd address pins, starting with A1 on the AM186CC microcontroller connecting to MA0 on the DRAM. The correct row and column addresses are generated on these odd address pins during a DRAM access. The RAS pins are multiplexed with LCS and MCS3, allowing a DRAM bank to be present in either high or low memory space. The MCS2 and MCS1 function as the upper and lower CAS pins, respectively, and define which byte of data in a 16-bit DRAM is being accessed. The AM186CC microcontroller supports the most common DRAM refresh option, CAS-Before-RAS. All refresh cycles contain three wait states to support the DRAMs at various frequencies. The DRAM controller never performs a burst access. All accesses are single accesses to DRAM. If the PCS chip selects are decoded to be in the DRAM address range, PCS accesses take precedence over the DRAM. Chip Selects The AM186CC microcontroller provides six chip select outputs for use with memory devices and eight more for use with peripherals in either memory or I/O space. The six memory chip selects can be used to address three memory ranges. Each peripheral chip select addresses a 256-byte block offset from a programmable base address. The AM186CC microcontroller can be programmed to sense a ready signal for each of the peripheral or memory chip select lines. A bit in each chip select control register determines whether the external ready signal is required or ignored. The chip selects can control the number of wait states inserted in the bus cycle. Although most memory and peripheral devices can be accessed with three or less wait states, some slower devices cannot. This feature allows devices to use wait states to slow down the bus.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19-A0) is valid onehalf CLKOUT cycle in advance of the address on the AD bus. When used in conjunction with the modified UCS and LCS outputs and the byte write enable signals, the A19-A0 bus provides a seamless interface to exter nal SRAM, and Flash memor y/EPROM systems.
Byte Write Enables
The AM186CC microcontroller provides the WHB (Write High Byte) and WLB (Write Low Byte) signals that act as byte write enables. WHB is the logical OR of BHE and WR. WHB is Low when both BHE and WR are Low. WLB is the logical OR of A0 and WR. WLB is Low when A0 and WR are both Low. T h e b y t e w r i t e e n a b l e s a r e d r i ve n w i t h t h e nonmultiplexed address bus as required for the write timing requirements of common SRAMs.
Output Enable
The AM186CC microcontroller provides the RD (Read) signal which acts as an output enable for memory or peripheral devices. The RD signal is Low when a word or byte is read by the AM186CC microcontroller. DRAM Support To support DRAM, the AM186CC microcontroller has a fully integrated DRAM controller that provides a glueless interface to 25-70-ns Extended Data Out (EDO) DRAM. (EDO DRAM is sometimes called Hyper-Page Mode DRAM.) Up to two banks of 4-Mbit (256 Kbit x 16 bit) DRAM can be accessed. Page Mode DRAM, Fast Page 34
Am186TMCC Communications Controller Data Sheet
The chip select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit. General enhancements over the original 80C186 include bus mastering (three-state) support for all chip selects and activation only when the associated register is written, not when it is read.
Clock Control
The processor supports clock rates from 16 to 50 MHz using an integrated cr ystal oscillator and PLL. Commercial and industrial temperature ratings are available. Separate cr ystal oscillator inputs are provided for the USB and CPU. Flexibility is provided to run the entire device from a 12-, or 24-MHz crystal when the USB is in use. The CPU can run in 1x, 2x, or 4x mode; USB can run in 2x or 4x mode.
t2 t3 Data Phase t4
t1 Address Phase
CLKOUT A19-A0 Address
AD15-AD0 (Read)
Address
Data
AD15-AD0 (Write) LCS or UCS
Address
Data
MCSx, PCSx
Figure 3.
AM186CC Controller Address Bus -- Default Operation
Am186TMCC Communications Controller Data Sheet
35
t1 Address Phase CLKOUT A19-A0 AD7-AD0 (Read) AD15-AD8 (Read) AD15-AD0 (Write) LCS or UCS
t2
t3 Data Phase
t4
Address
Data Data
Data
Figure 4.
AM186CC Controller--Address Bus Disable In Effect
36
Am186TMCC Communications Controller Data Sheet
In-Circuit Emulator Support
Because pins are an expensive resource, many play a dual role, and the programmer selects PIO operation or an alternate function. However, a pin configured to be a PIO may also be required for emulation support. Therefore, it is impor tant that before a design is committed to hardware, a user should contact potential emulator suppliers for a list of their emulator's pin r e q ui r em e n ts. T he fo l l owi n g P I O s i gn a l s ar e multiplexed with alternate signals that may be used by emulators: PIO8, PIO15, PIO33-PIO35.
The AM186CC microcontroller was designed to minimize conflicts. In most cases, pin conflict is avoided. For example, if the ALE signal is required for m u l t i p l ex b u s s u p p o r t , t h e n i t w o u l d n o t b e programmed as PIO33. If the multiplexed AD bus is not used, then ALE can be programmed as a PIO pin. If the multiplexed bus is not in use, then the emulator does not require the ALE signal. However, an emulator is likely to always use the de-multiplexed address, regardless of how the AD bus is programmed.
APPLICATIONS
The AM186CC microcontroller, with its integrated HDLC, USB, and other communications features, provides a highly integrated, cost-effective solution for a wide range of telecommunications and networking applications. n ISDN Modems and Terminal Adapters: Nextgeneration ISDN equipment requires USB (or HighSpeed UART capability), in addition to three channels of HDLC. n Low-End Routers: ISDN to Ethernet-based personal routers, often used for connections in Small Office/Home Office (SOHO) environments, require three channels of HDLC, as well as the high performance of a 16-bit controller. n Linecard Applications: Typically, linecards used in Central Offices (COs), PABX equipment, and other telephony applications require one or two channels of HDLC. Linecard manufacturers are moving to more lines per card for analog POTS as a means of cost reduction. This, and digital linecards for support of ISDN, often require higher performance than existing 8-bit devices can offer. The AM186CC microcontroller is an ideal solution for these applications because it integrates much of the necessary glue logic while providing higher performance. n xDSL Applications: Today's xDSL applications, such as high-speed ADSL modems, require data handling of 2 Mbit/s or greater and can take advantage of the USB interface for easy connectivity to the PC. n Digital Corded Phones: Typical digital telephone applications use up to three channels of HDLC and may use USB for merged PC telephony applications. n Industrial Control: Embedded x86 processors have long been used in the industrial control market. These applications often require a robust, highperformance processor solution with one or two channels of HDLC. n USB Peripheral Devices: These devices will become more common as the PC market embraces the USB protocol. In addition to implementing communications device class systems such as an ISDN terminal adapter, the USB controller makes the AM186CC microcontroller suitable for certain PC desktop applications such as a USB camera interface, ink-jet printers, and scanners. n General Communications Applications: The AM186CC microcontroller will also find a home in general embedded applications, because many devices will incorporate communications capability in the future. Many designs are adding HDLC capability as a robust means of inter- and intra-system communications. The AM186CC microcontroller is especially attractive for 186 designs adding HDLC, USB, or both. Block diagrams on the following pages show some typical AM186CC microcontroller designs: Figure 5 on page 38 shows an ISDN terminal adapter system application, Figure 6 on page 38 shows an ISDN to Ethernet low-end router application, and Figure 7 on page 39 shows a 32-channel linecard application. The ISDN ter minal adapter features an S/T or U interface and either a High-Speed UART or USB connection for attaching the modem to the PC. The ISDN-to-Ethernet low-end router features an S/T or U interface, two POTS lines, and a 10-Mbit/s connection to the PC. The 32-channel linecard design demonstrates the AM186CC microcontroller's us e in a linecard application where 32 incoming POTS lines are aggregated onto a single E1 connection.
Am186TMCC Communications Controller Data Sheet
37
I
Figure 5.
ISDN Terminal Adapter System Application
Figure 6. ISDN to Ethernet Low-End Router System Application
38
Am186TMCC Communications Controller Data Sheet
Figure 7.
32-Channel Linecard System Application
Am186TMCC Communications Controller Data Sheet
39
CLOCK GENERATION AND CONTROL
The AM186CC controller clocks include the general system clock (CLKOUT), USB clock, transmitter/ receiver clocks for each HDLC channel, and the baud rate generator clock for UART and High-Speed UART. The SSI and the timers (Timers 0, 1, and 2) derive their clocks from the system clock.
from 8 to 40 MHz, depending on the PLL mode selected and the desired system frequency (see Figure 9 on page 42). The system PLL modes are chosen by the state of the {CLKSEL1} and {CLKSEL2} pins during reset. For thes e pins trap se ttings see Table 31 , "Res et Configuration Pins (Pinstraps)," on page A-10. The system clock can be generated in one of two ways: n Using the internal PLL running at 1x, 2x, or 4x the reference clock. The reference clock can be generated from an external crystal using the integrated oscillator or an external oscillator input. n Bypassing the internal PLL. The external reference generated from either a crystal or an external oscillator input is used to generate the system clock. For more information about bypassing the internal PLL, refer to "PLL Bypass Mode" on page 43.
Features
The AM186CC controller clocks include the following features and characteristics: n Two independent crystal-controlled oscillators that use exter nal fundamental mode cr ystals or oscillators to generate the system input clock and the USB input clock. n Two independent internal PLLs, one of which generates a system clock (CLKOUT) that is 1x, 2x, or 4x the system input clock, and one that generates the 48-MHz clock required for the USB from either a 48-, 24-, or 12-MHz input. n Single clock source operation possible by sharing the clock source between the system and the USB. n Each HDLC receives its clock inputs directly from the external communication clock pins (TCLK _X and RCLK_X) in all modes except in GCI mode. In GCI mode the external GCI communication clocks (TCLK_A and RCLK_A) are first converted to an internal clocking format (analogous to PCM Highway) before presentation to the HDLC. The system clock must be at least the same frequency as any HDLC clock. - HDLC DCE mode supports clocks up to 10 MHz. - HDLC PCM mode supports clocks up to 10 MHz. - HDLC GCI mode supports a 1.536-MHz clock input. (System clock must be at least twice the GCI clock.) n SSI clock (SCLK) is derived from the system clock, divided by 2, 4, 8, 16, 32, 64, 128, or 256. n Timers 0 and 1 can be configured to be driven by the timer input pins (TMRIN1, TMRIN0) or at onefourth of the system clock. Timer 2 is driven at onefourth of the system clock. n UART clock can be derived from the internal system clock frequency or from the UART clock (UCLK) input. See Figure 8 on page 41 for a diagram of the basic clock generation and Figure 9 on page 42 for suggested clock frequencies and modes.
USB Clock
The USB PLL provides the 48-MHz clock that is required for USB full-speed operation. This clock is divided down to provide a 12-MHz clock that supports the full-speed USB rate (12 Mbit/s). The low-speed rate of 1.5 Mbit/s is not supported. The USB PLL modes are chosen by the state of the {USBSEL1} and {USBSEL2} pins during reset. For these pinstrap settings, refer to Table 31, "Reset Configuration Pins (Pinstraps)," on page A-10. The USB clock can be generated in one of two ways: n Using the system clock. In this mode, the system PLL is restricted to 48-MHz operation only.
Note: When using the system clock for the USB clock source, the designer must externally pull down the USBX1 input.
n Using its own internal 48-MHz PLL. This PLL can run in 2x or 4x mode and requires a 12- or 24-MHz reference that can be generated by either the integrated cr ystal-controlled oscillator or an external oscillator input.
Note: The system clock must be a minimum of 24 MHz when using the USB peripheral controller and its internal 48-MHz PLL.
The USB specification requires a frequency tolerance of less than 2500 ppm, which must be met whether using an external clock source, a crystal on USBX1- USBX2, or clock sharing by system and USB. When using a crystal, some frequency tolerance margin must be allowed to account for the differences in external loading capacitances, etc. The usual rule of thumb is to specify a crystal with a frequency tolerance of one half the required frequency tolerance.
System Clock
The system PLL generates frequencies from 16 to 50 MHz. The reference for the system PLL can vary
40
Am186TMCC Communications Controller Data Sheet
Clock Sharing by System and USB
The system and USB clocks can be generated from a single source in one of two ways: n The system can run at 48 MHz by using the system clock for the USB clock.
n The system can be run at 24 MHz by sharing an exter nal clock reference (X1) with the USB (USBX1). A 12-MHz source can be used with the system PLL in 2x mode and the USB PLL in 4x mode, or a 24-MHz source can be used with the system in 1x mode and the USB in 2x mode.
Note: When using the system clock for the USB clock source, the designer must externally pull down the USBX1 input.
AM186CC Controller 1x PLL 2x 4x PLL Bypass Mode {CLKSEL2}-{CLKSEL1} System Clock CLKOUT
X1
X2
USBX1
USBX2 PLL
2x 4x
48-MHz USB Clock
{USBSEL2}-{USBSEL1}
Figure 8.
System and USB Clock Generation
Am186TMCC Communications Controller Data Sheet
41
System Operating Frequency 0 MHz 16 MHz 4x Mode 20 MHz 24 MHz 30 MHz 32 MHz
8-MHz to 12.5-MHz Xtal or Clock
40 MHz
50 MHz
2x Mode
8-MHz to 25-MHz Xtal or Clock
1x Mode
16-MHz to 40-MHz Xtal or Clock1
PLL Bypass Mode
0-MHz to 24-MHz Xtal or Clock
PLL Bypass Mode
1The
1x Mode
2x Mode
4x Mode
crystal oscillator is not guaranteed above 40 MHz.
Figure 9.
Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies
Crystal-Driven Clock Source
The internal oscillator circuit is designed to function with an external parallel-resonant fundamental mode crystal. The crystal frequency can vary from 8 to 40 MHz, depending on the PLL mode selected and desired system frequency. When selecting a crystal, the load capacitance should always be specified (C L ). This value can cause variance in the oscillation frequency from the desired specified value (resonance). The load capacitance and the loading of the feedback network have the following relationship: CL = (C1 C2) + CS (C1 + C2) where CS is the stray capacitance of the circuit. Table 6 shows crystal parameter values. Figure 10 shows the system clocks using an external crystal and the integrated oscillator. The specific values for C 1 and C 2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design.
C1 Parameter Frequency ESR 8-24 MHz 24-50 MHz
Table 6. Crystal Parameters
Min. Value 8 20 20 10 Max. Value 40 90 60 -- Units MHz ohms ohms pF
Load Capacitance
X1/USBX1 Xtal X2/USBX2 C2
Figure 10. External Interface to Support Clocks-- Fundamental Mode Crystal
42
Am186TMCC Communications Controller Data Sheet
External Clock Source
The internal oscillator also can be driven by an external clock source. The external clock source should be connected to the input of the inverting amplifier (X1 or USBX1) with the output (X2 or USBX2) left unconnected. Figure 11 shows the system clocks using an external clock source (oscillator bypass).
When changing frequency in PLL Bypass mode, the X1 input must not have any short or "runt" pulses. At 24 MHz, the nominal High/Low time is 21 ns. The actual High times and Low times must not fall below 16 ns. These values allow a 60%/40% duty cycle at X1. In the AM186CC microcontroller, the system clock must be at the same or a greater frequency than the HDLC clock and UCLK (if using UCLK). Therefore, if reducing the system clock frequency, disable these interfaces or run them at a lower frequency. The USB PLL and USBX1 determine the USB clock. USB requires the system clock to be 24 MHz or greater. Therefore, disable the USB peripheral controller before slowing the system clock to less than 24 MHz. If USB is not used, the USBX1 can be pulled down.
Note: X1, X2, USBX1, and USBX2 are not 5-V tolerant and have a maximum input equal to VCC.
External Clock NC
X1/USBX1
X2/USBX2
Figure 11.
External Interface to Support Clocks-- External Clock Source
UART Baud Clock
The UARTs (low- and high-speed) have two possible clock sources: the system clock or the UCLK input pin. If UCLK is used for the UART clock, the system clock must be at least the same frequency as UCLK. The clock configurations are shown graphically in Figure 12. The baud clock is generated by dividing the clock source by the value of baud rate divisor register. The serial port logic can select its baud rate clock from either an external pin (UCLK) or from the system clock. The system or UCLK clock is selected independent of any other settings. The formula for determining the baud rate divisor register value is: BAUDDIV = (clock frequency/(16 * baud rate))
Static Operation
The AM186CC controller is a fully static design and can be placed in static mode by stopping the input clock. PLL bypass mode must be used with an external clock source. For PLL bypass mode, refer to the PLL Bypass Mode discussion below.
Note: It is the responsibility of the system designer to ensure that no short clock phases are generated when starting or stopping the clock.
PLL Bypass Mode
The Am 186CC microcontroller provides a PLL Bypass mode that allows the X1 input frequency to be anywhere from 0 to 24 MHz. When the microcontroller is in PLL Bypass mode, the CLKOUT frequency equals the X1 input frequency. This mode must be used with an external clock source. For PLL Bypass mode enabling, refer to Table 31, "Reset Configuration Pins (Pinstraps)," on page A-10.
Note: UCLK cannot be clocked at a frequency higher than the system cock frequency.
System Clock UCLK UART/High-Speed UART Clock Select Baud Divisor
Oversample Clock
Divide for Oversampling
Baud Clock
Autobaud Clock (High-Speed UART Only)
Figure 12.
UART and High-Speed UART Clocks
Am186TMCC Communications Controller Data Sheet
43
POWER SUPPLY OPERATION
CMOS dynamic power consumption is proportional to the square of the operating voltage multiplied by capacitance and operating frequency. Static system operation can reduce power consumption by enabling the system designer to reduce operating frequency when possible. However, operating voltage is always the dominant factor in power consumption. By reducing the operating voltage from 5 V to 3.3 V for any device, the power consumed is reduced by 56%. Reduction of system logic operating voltage dramatically reduces overall system power consumption. Additional power savings can be realized as low-voltage mass storage and peripheral devices become available. Two basic strategies exist in designing systems containing the AM186CC controller. The first strategy is to design a homogenous system in which all logic components operate at 3.3 V. This provides the lowest overa ll power consumpti on. However, s ys tem designers may need to include devices for which 3.3-V versions are not available. In the second strategy, the system designer must then design a mixed 5-V/3.3-V system. This compromise enables the system designer to minimize the system logic power consumption while still including the functionality of the 5-V features. The choice of a mixed voltage system design also involves balancing design complexity with the need for the additional features. n Preferably, all inputs are driven by sources that can be three-stated during a system reset condition. The system reset condition should persist until stable V CC conditions are met. This should help ensure that the maximum input levels are not exceeded during power-up conditions. n Preferably, all pullup resistors are tied to the 3.3-V supply, which ensures that inputs requiring pullups are not over stressed during power-up.
PIO Supply Current Limit
Each programmable I/O output is able to sink or source a sustained 16-mA drive current. However, only 40 mA of sustained PIO current is allowed for each supply pin (VCC), and only 60 mA is allowed for each ground pin (VSS). To calculate the PIO current for each supply or ground pin, sum the applicable current (source or sink) of all PIO pins on either side of the pin (to the adjacent corresponding pins), and divide the sum by two. The resulting value should not exceed 40 mA for VCC or 60 mA for VSS. Exclude the following pins from this calculation: 72 ( V S S _ A) , 82 ( V S S _U SB ) , 77 ( V C C _A ) , an d 7 9 (VCC_USB). For example, to calculate the PIO current for pin 83 (VSS), total the sustained sinking current for all PIO pins between pin 71 (V SS ) and pin 100 (V SS ), and divide the sum by two.
Power Supply Connections
Connect all V CC pins together to the 3.3-V power supply and all ground pins to a common system ground.
Input/Output Circuitry
To accommodate current 5-V systems, the AM186CC controller has 5-V tolerant I/O drivers. The drivers produce TTL-compatible drive output (minimum 2.4-V logic High) and receive TTL and CMOS levels (up to VCC + 2.6 V). The following are some design issues that should be considered with mixed 3.3-V/5-V designs: n During power-up, if the 3.3-V supply has a significant delay in achieving stable operation relative to 5-V supply, then the 5-V circuitry in the system may start driving the processor's inputs above the maximum levels (V CC + 2.6 V). The system design should ensure that the 5-V supply does not exceed 2.6 V above the 3.3-V supply during a power-on sequence.
44
Am186TMCC Communications Controller Data Sheet
ABSOLUTE MAXIMUM RATINGS1
Parameter Temperature under bias: Commercial Industrial Storage temperature Voltage on 5-V-tolerant pins with respect to ground Voltage on other pins with respect to ground Sustained PIO current on any supply (VCC) Sustained PIO current on any ground (VSS) pin5 pin5
4
Symbol TC2 TA3 -- -- -- -- --
Minimum 0 -40 -65 -0.5 -0.5 40 60
Maximum 100 +85 +150 VCC + 2.6 VCC + 0.5 -- --
Unit C C C V V mA mA
Notes: 1. Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2. TC = case temperature. 3. TA = ambient temperature. 4. 5 V-tolerant pins are indicated in Table 35, "Pin List Summary," on page A-12. 5. See "PIO Supply Current Limit" on page 44.
OPERATING RANGES1
Parameter Commercial Industrial Supply voltage with respect to ground Symbol TC2 TA3 VCC Minimum 0 -40 3.0 Maximum 100 + 85 3.6 Unit C C V
Notes: 1. Operating Ranges define those limits between which the functionality of the device is guaranteed. 2. TC = case temperature. 3. TA = ambient temperature.
DRIVER CHARACTERISTICS--UNIVERSAL SERIAL BUS
Each USBD+ and USBD- pin connects through a series resistor directly to the USB. The series resistor value should be selected to achieve a total driver impedance between 29 and 44 ohms, as required by the USB Version 1.0 specification. A 36-W 1% series resistor is recommended for each pin. Characteristics of these two pins are defined in the U S B Ve r s i o n 1 . 0 s p e c i f i c a t i o n . C o n s u l t t h i s specification for details about overall USB system design. (At the time of this writing, the current USB specification and related information can be obtained on the Web at www.usb.org.) The AM186CC controller is guaranteed to meet all USB specifications. Required analog transceivers are integrated into the AM186CC controller.
Am186TMCC Communications Controller Data Sheet
45
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES1
Symbol VOH VOH VOL VIH5 VIH VIL ILI ILO PCC Parameter Output High voltage (IOH = -2.4 mA) Output High voltage (IOH = -0.1 mA) Output Low voltage (IOL = 4.0 mA) 5-V tolerant Input High voltage Input High voltage, except 5-V tolerant Input Low voltage Input leakage current (0.1 V VOUT VCC) (All pins except those with internal pullup/pulldown resistors) Output leakage current3 (0.1 V VOUT VCC) Power consumption
2
Preliminary Minimum 2.4 VCC - 0.2 -- 2.0 2.0 -0.3 -- -- -- Maximum -- -- 0.45 VCC + 2.6 VCC+0.3 0.8 10 15 1.2
Unit V V V V V V mA mA W
Notes: 1. Current out of pin is stated as a negative value. 2. Characterized but not tested. 3. This parameter is for three-state outputs where VOUT is driven on the three-state output.
CAPACITANCE
Symbol CIN CCLK COUT CI/O Parameter Input capacitance Clock capacitance Output capacitance I/O pin capacitance Preliminary Minimum -- -- -- -- Maximum 15 15 20 20 Unit pF pF pF pF
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Am186TMCC Communications Controller Data Sheet
MAXIMUM LOAD DERATING
All maximum delay numbers should be increased by 0.035 ns for every pF of load (up to a maximum of 150 pF) over the maximum load specified in Table 35, "Pin List Summary," on page A-12.
n No DC loads on the output buffers n Output capacitive load set to 30 pF n AD bus set to data only n PIOs are disabled n Timer, serial port, refresh, and DMA are enabled Table 7 shows the values that are used to calculate the typical power consumption value for the AM186CC controller. Table 7.
MHz 25 40 50
POWER SUPPLY CURRENT
For the following typical system specification shown in Figure 13, ICC has been measured at 6 mA per MHz of system clock. The typical system is measured while the system is executing code in a typical application with nominal voltage and maximum case temperature. Actual power supply current is dependent on system design and may be greater or less than the typical ICC figure presented here. Typical current in Figure 13 is given by: ICC = 6 mA 1/4 freq(MHz) Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were set to the following modes:
Typical Power Consumption Calculation
Typical ICC 6 6 6 Volts 3.3 3.3 3.3 Typical Power in Watts 0.495 0.792 0.99
MHz 1/4 ICC 1/4 Volts / 1000 = P
320 280 240 200
ICC (mA) 160
120 80 40 0 10 20 30 40 50
Clock Frequency (MHz)
Figure 13. Typical Icc Versus Frequency
Am186TMCC Communications Controller Data Sheet
47
THERMAL CHARACTERISTICS PQFP Package
The AM186CC controller is specified for operation with case temperature ranges from 0C to +100C for 3.3 V 0.3 V (commercial). Case temperature is measured at the top center of the package as shown in Figure 14. The various temperatures and thermal resistances can be determined using the equations in Figure 15 with information given in Table 8. The total thermal resistance is qJA; qJA is the sum of qJC, the internal thermal resistance of the assembly, and qCA, the case to ambient thermal resistance.
The variable P is power in watts. Power supply current (ICC) is in mA per MHz of clock frequency. qJA TC q JC qCA
qJA = qJC + qCA Figure 14. Thermal Resistance(C/Watt)
TJ = TC + (P 1/4 qJC) TJ = TA + (P 1/4 qJA) TC = TJ - (P TC = TA + (P
qJA = qJC + qCA P = ICC 1/4 freq (MHz) 1/4 VCC
1/4 qJC) 1/4 qCA) TA = TJ - (P 1/4 qJA) TA = TC - (P 1/4 qCA)
Figure 15.
Thermal Characteristics Equations
Table 8.
Thermal Characteristics (C/Watt)
Airflow (Linear Feet per Minute) 0 fpm 200 fpm 400 fpm 600 fpm
Package/Board PQFP/2-Layer
qJC 7 7 7 7 5 5 5 5
qCA 38 32 28 26 18 16 14 12
qJA 45 39 35 33 23 21 19 17
PQFP/4-Layer to 6-Layer
0 fpm 200 fpm 400 fpm 600 fpm
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Am186TMCC Communications Controller Data Sheet
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. These periods are referred to as time states. A typical bus cycle is composed of four consecutive time states: t1, t2, t3, and t4. Wait states, which represent multiple t3 states, are referred to as tw states. When no bus cycle is pending, an idle (ti) state occurs. I n th e sw i t c h i ng pa r a me t e r d e s c r i p ti o n s, t h e multiplexed address is referred to as the AD address bus; the demultiplexed address is referred to as the A address bus. Figure 16 defines symbols used in the switching waveform diagrams. Table 9 on page 50 contains an alphabetical listing of the switching parameter symbols, and Table 10 on page 54 contains a numerical listing of the switching parameter symbols.
WAVEFORM
INPUT Must be Steady May change from H to L or from H to threestate May change from L to H or from L to threestate
OUTPUT Will be Steady Will be changing from H to L or from H to three-state Will be changing from L to H or from L to threestate
Figure 16. Key to Switching Waveforms
Am186TMCC Communications Controller Data Sheet
49
Table 9. Alphabetical Key to Switching Parameter Symbols
Parameter Symbol tARYCH tARYCHL tARYHDSH tARYHDV tARYLCL tARYLDSH tAVBL tAVCH tAVLL tAVRL tAVWL tAZRL tCH1CH2 tCHAV tCHCAS tCHCK tCHCL tCHCSV tCHCSX tCHCTV tCHCV tCHCZ tCHDX tCHLH tCHLL tCHQ0SV tCHQ1SV tCHRAS tCHRFD tCHSV tCICO tCKHL tCKIN tCKLH tCL2CL1 tCLARX tCLAV tCLAX tCLAZ tCLCH tCLCK tCLCL tCLCLX No. 49 51 95 89
1 1
Description ARDY resolution transition setup time ARDY inactive holding time ARDY High to DS High ARDY assert to data valid ARDY setup time ARDY Low to DS High A address valid to WHB, WLB Low AD address valid to clock High AD address valid to ALE Low A address valid to RD Low A address valid to WR Low AD address float to RD active CLKOUT rise time CLKOUT High to A address valid Change in CAS delay X1 High time CLKOUT High time CLKOUT High to LCS/UCS valid MCS/PCS inactive delay Control active delay 2 Command lines valid delay (after float) Command lines float delay Status hold time ALE active delay ALE inactive delay Queue status 0 output delay Queue status 1 output delay Change in RAS delay CLKOUT High to RFSH valid Status active delay X1 to CLKOUT skew X1 fall time X1 period X1 rise time CLKOUT fall time ARDY active hold time AD address and BHE valid delay Address hold AD address float delay CLKOUT Low time X1 Low time CLKOUT period LCS inactive delay
52 961 87 14 12 66 65 24 45 68 404 38 44 67 18 22 64 63 8 9 11 55 56 403 791 3 69 39 36 40 46 50 5 6 15 43 37 42 801
50
Am186TMCC Communications Controller Data Sheet
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter Symbol tCLCSL tCLCSV tCLDOX tCLDV tCLDX tCLHAV tCLRF tCLRH tCLRL tCLSH tCLSRY tCLTMV tCOLV tCSHARYL tCVCTV tCVCTX tCVDEX tCXCSX tDSHDIR tDSHDIW tDSHDX tDSHLH tDSLDD tDSLDV tDVCL tDVDSL tDXDL tHVCL tINVCH tLCRF tLHAV tLHLL tLLAX tLRLL tRESIN tRFCY tRHAV tRHDX tRHDZ tRHLH tRLRH tSRYCL No. 811 16 30 7 2 62 821 27 25 4 48 54 402 881 20 31 21 17 92 98 93
1 1 1
Description LCS active delay MCS/PCS active delay Data hold time Data valid delay Data in hold HLDA valid delay CLKOUT High to RFSH invalid RD inactive delay RD active delay Status and BHE inactive delay SRDY transition hold time Timer output delay Column address valid delay Chip select to ARDY Low Control active delay 1 Control inactive delay DEN/DS inactive delay MCS/PCS hold from command inactive DS High to data invalid--read DS High to data invalid--write DS High to data bus turn-off time DS inactive to ALE inactive DS Low to data driven DS Low to data valid Data in setup Data valid to DS Low DEN/DS inactive to DT/R Low HOLD setup Peripheral setup time LCS inactive to RFSH active delay ALE High to address valid ALE width AD address hold from ALE inactive LCS precharge pulse width RES setup time RFSH cycle time RD inactive to AD address active RD High to data hold on AD bus RD High to data bus turn-off time RD inactive to ALE High RD pulse width SRDY transition setup time
41 901 911 1 971 19 58 53 861 23 10 13 841 57 851 29 59 941 28 26 47
Am186TMCC Communications Controller Data Sheet
51
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter Symbol tWHDEX tWHDX tWHLH tWLWH tUCHCK tUCKHL tUCKIN tUCKLH tUCLCK tF tJR1 tJR2 tR DCE tTCLKH tTCLKHD tTCLKL tTCLKO tTCLKPER tTCLKR tTCLKSU PCM (Slave) tCLKP tDCD tDCLT tDCT tDFT tDTW tDZF tDZF tHCD tHCF tHFI tSUDC tSUFC tSYNSS tWH tWL tWSYN tDTZ 1 8 13 11 12 17 5 6 10 4 14 9 7 15 2 3 16 18 PCM clock period Delay time from CLK High to TXD valid Delay from CLK Low of last bit to TSC invalid Delay to TSC valid from CLK Delay to TSC valid from FSC Delay from last bit CLK Low to TXD weak drive Delay time to valid TXD from CLK Delay time to valid TXD from FSC Hold time from CLK Low to RXD invalid Hold time from CLK Low to FSC valid Hold time from CLK Low to FSC invalid Setup time from RXD valid to CLK Setup time for FSC High to CLK Low Time between successive synchronization pulses PCM clock High PCM clock Low FSC width invalid Delay from last bit CLK (plus one) High to TXD disable 2 6 3 4 1 7 5 DCE clock High DCE clock hold DCE clock Low DCE clock to output delay DCE clock period DCE clock rise/fall DCE clock setup No. 35 34 33 32 3 4 1 5 2 2 3 4 1 Description WR inactive to DEN inactive Data hold after WR WR inactive to ALE High WR pulse width USBX1 High time USBX1 fall time USBX1 period USBX1 rise time USBX1 Low time Fall time Consecutive transition jitter Paired transition jitter Rise time
USB Timing (Clocks)
USB Timing (Data/Jitter)
52
Am186TMCC Communications Controller Data Sheet
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter Symbol PCM (Master) tDCFH tDCFL GCI tDHC tDSC tDSF tFD tFH tHD tSD tSF tWFH tWH tWL SSI tCLEV tCLSL tDVSH tSHDX tSLDV 1 2 3 4 5 CLKOUT Low to SDEN valid CLKOUT Low to SCLK Low Data valid to SCLK High SCLK High to data invalid SCLK Low to data valid 9 7 8 5 4 11 10 3 6 1 2 Data hold/clock Data delay/clock Data delay/FSC Frame delay/clock Frame hold/clock Data hold Data setup Frame setup Frame width High Pulse width High Pulse width Low 1 2 Delay time from CLK High to FSC High Delay time from CLK High to FSC Low No. Description
Notes: 1. Specification defined but not in use at this time.
Am186TMCC Communications Controller Data Sheet
53
Table 10.
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Numerical Key to Switching Parameter Symbols
Description Data in setup Data in hold Status active delay Status and BHE inactive delay AD address and BHE valid delay Address hold Data valid delay Status hold time ALE active delay ALE width ALE inactive delay AD address valid to ALE Low AD address hold from ALE inactive AD address valid to clock High AD address float delay MCS/PCS active delay MCS/PCS hold from command inactive MCS/PCS inactive delay DEN/DS inactive to DT/R Low Control active delay 1 DEN/DS inactive delay Control active delay 2 ALE High to address valid AD address float to RD active RD active delay RD pulse width RD inactive delay RD inactive to ALE High RD inactive to AD address active Data hold time Control inactive delay WR pulse width WR inactive to ALE High Data hold after WR WR inactive to DEN inactive X1 period X1 Low time X1 High time X1 fall time X1 rise time DS inactive to ALE inactive CLKOUT period CLKOUT Low time
Parameter Symbol tDVCL tCLDX tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLAZ tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCVDEX tCHCTV tLHAV tAZRL tCLRL tRLRH tCLRH tRHLH tRHAV tCLDOX tCVCTX tWLWH tWHLH tWHDX tWHDEX tCKIN tCLCK tCHCK tCKHL tCKLH tDSHLH tCLCL tCLCH
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Am186TMCC Communications Controller Data Sheet
Table 10.
No. 44 45 46 47 48 49 50 51 52 53 54 54 56 57 58 59 62 63 64 65 66 67 68 69 79 801 81 82 84 86
1 1 1
Numerical Key to Switching Parameter Symbols (Continued)
Description CLKOUT High time CLKOUT rise time CLKOUT fall time SRDY transition setup time SRDY transition hold time ARDY resolution transition setup time ARDY active hold time ARDY inactive holding time ARDY setup time Peripheral setup time DRQ setup time Timer output delay Queue status output delay RES setup time HOLD setup RD High to data hold on AD bus HLDA valid delay Command lines float delay Command lines valid delay (after float) A address valid to WR Low A address valid to RD Low CLKOUT High to LCS/UCS valid CLKOUT High to A address valid X1 to CLKOUT skew CLKOUT High to RFSH valid LCS inactive delay LCS active delay CLKOUT High to RFSH invalid LCS precharge pulse width RFSH cycle time LCS inactive to RFSH active delay A address valid to WHB, WLB Low Chip select to ARDY Low ARDY assert to data valid DS Low to data driven DS Low to data valid DS High to data invalid--read DS High to data bus turn-off time RD High to data bus turn-off time ARDY High to DS High ARDY Low to DS High Data valid to DS Low
Parameter Symbol tCHCL tCH1CH2 tCL2CL1 tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL tINVCH tINVCL tCLTMV tCHQSV tRESIN tHVCL tRHDX tCLHAV tCHCZ tCHCV tAVWL tAVRL tCHCSV tCHAV tCICO tCHRFD tCLCLX tCLCSL tCLRF tLRLL tRFCY tLCRF tAVBL tCSHARYL tARYHDV tDSLDD tDSLDV tDSHDIR tDSHDX tRHDZ tARYHDSH tARYLDSH tDVDSL
851
1 1 1
87
88 90
891
1 1 1
91 92 94 95 96
931
1 1 1
971
Am186TMCC Communications Controller Data Sheet
55
Table 10.
No. 981 402 403 404 1 2 3 4 5 1 2 3 4 DCE 1 2 3 4 5 6 7 PCM (Slave) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Numerical Key to Switching Parameter Symbols (Continued)
Description DS High to data invalid--write Column address valid delay Change in RAS delay Change in CAS delay USBX1 period USBX1 Low time USBX1 High time USBX1 fall time USBX1 rise time Rise time Fall time Consecutive transition jitter Paired transition jitter DCE clock period DCE clock High DCE clock Low DCE clock to output delay DCE clock setup DCE clock hold DCE clock rise/fall PCM clock period PCM clock High PCM clock Low Hold time from CLK Low to FSC valid Delay time to valid TXD from CLK Delay time to valid TXD from FSC Setup time for FSC High to CLK Low Delay time from CLK High to TXD valid Setup time from RXD valid to CLK Hold time from CLK Low to RXD invalid Delay to TSC valid from CLK Delay to TSC valid from FSC Delay from CLK Low of last bit to TSC invalid Hold time from CLK Low to FSC invalid Time between successive synchronization pulses FSC width invalid Delay from last bit CLK Low to TXD weak drive Delay from last bit CLK (plus one) High to TXD disable
Parameter Symbol tDSHDIW tCOLV tCHRAS tCHCAS tUCKIN tUCLCK tUCHCK tUCKHL tUCKLH tR tF tJR1 tJR2 tTCLKPER tTCLKH tTCLKL tTCLKO tTCLKSU tTCLKHD tTCLKR tCLKP tWH tWL tHCF tDZF tDZF tSUFC tDCD tSUDC tHCD tDCT tDFT tDCLT tHFI tSYNSS tWSYN tDTW tDTZ
USB Timing (Clocks)
USB Timing (Data/Jitter)
56
Am186TMCC Communications Controller Data Sheet
Table 10.
No.
Numerical Key to Switching Parameter Symbols (Continued)
Description
Parameter Symbol tDCFH tDCFL tWH tWL tSF tFH tFD tWFH tDSC tDSF tDHC tSD tHD tCLEV tCLSL tDVSH tSHDX tSLDV
PCM (Master) 1 2 GCI 1 2 3 4 5 6 7 8 9 10 11 SSI 1 2 3 4 5 CLKOUT Low to SDEN valid CLKOUT Low to SCLK Low Data valid to SCLK High SCLK High to data invalid SCLK Low to data valid Pulse width High Pulse width Low Frame setup Frame hold/clock Frame delay/clock Frame width High Data delay/clock Data delay/FSC Data hold/clock Data setup Data hold Delay time from CLK High to FSC High Delay time from CLK High to FSC Low
Notes: 1. Specification defined but not in use at this time.
Am186TMCC Communications Controller Data Sheet
57
Switching Characteristics over Commercial and Industrial Operating Ranges
In this section the following timings and timing waveforms are shown: n Read (page 58) n Write (page 61) n Software halt (page 64) n Peripheral (page 65) n Reset (page 66) n External ready (page 68) n Bus hold (page 69) n System clocks (page 71) n USB clocks (page 72) n GCI bus (page 73) n PCM highway (slave) (page 74) n PCM highway (master) (page 76) n DCE interface (page 77) n USB (page 78) n SSI (page 79) n DRAM (page 80) Table 11. Read Cycle Timing1
Preliminary Parameter No. 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol tDVCL tCLDX tCHSV tCLSH tCLAV tCLAX tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLAZ tCLCSV tCXCSX tCHCSX tDXDL tCVCTV Description Data in setup Data in hold2 25 MHz Min 10 3 0 0 0 0 0 -- tCLCL-10=30 -- 0.5 * tCLCH tCHCL 0 tCLAX=0 0 tCLCH 0 -1 0 Max -- -- 20 20 20 -- -- 20 -- 20 -- -- -- 20 20 -- 20 -- 20 40 MHz Min 5 2 0 0 0 0 0 -- tCLCL-5=20 -- 0.5 * tCLCH tCHCL 0 tCLAX=0 0 tCLCH 0 -1 0 Max -- -- 12 12 12 -- -- 12 -- 12 -- -- -- 12 12 -- 12 -- 12 50 MHz (Commercial Only) Min 5 2 0 0 0 0 0 -- tCLCL-5=15 -- 0.5 * tCLCH tCHCL 0 tCLAX=0 0 tCLCH 0 -1 0 Max -- -- 10 10 10 -- -- 10 -- 10 -- -- -- 10 10 -- 10 -- 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
General Timing Requirements
General Timing Responses Status active delay Status and BHE inactive delay AD address and BHE valid delay Address hold Status hold time ALE active delay ALE width ALE inactive delay AD address valid to ALE Low3 AD address hold from ALE inactive3 AD address valid to clock High AD address float delay MCS/PCS active delay MCS/PCS hold from command inactive MCS/PCS inactive delay DEN/DS inactive to DT/R Low3, 4 Control active delay 1
58
Am186TMCC Communications Controller Data Sheet
Table 11.
Parameter No. 21 22 23 Symbol tCEVDX tCHCTV tLHAV Description DEN/DS inactive delay4 Control active delay 2 ALE High to address valid AD address float to RD active RD active delay RD pulse width RD inactive delay RD inactive to ALE High3 RD inactive to AD address active 3 RD High to data hold on AD Bus2 A address valid to RD Low CLKOUT High to LCS/UCS valid CLKOUT High to A address valid
Read Cycle Timing1 (Continued)
Preliminary 25 MHz 40 MHz Max 20 20 -- Min 0 0 7.5 Max 12 12 -- 50 MHz (Commercial Only) Min 0 0 5 Max 10 10 -- ns ns ns Unit
Min 0 0 15
Read Cycle Timing Responses 24 25 26 27 28 29 59 66 67 68 tAZRL tCLRL tRLRH tCLRH tRHLH tRHAV tRHDX tAVRL tCHCSV tCHAV 0 0 2tCLCL-15=65 0 tCLCH-3 tCLCL-10=30 3 1.5tCLCL-15=45 0 0 -- 20 -- 20 -- -- -- -- 20 20 0 0 2tCLCL-10=40 0 tCLCH-2 tCLCL-5=20 2 1.5tCLCL-10= 27.5 0 0 -- 10 -- 12 -- -- -- -- 10 10 0 0 2tCLCL-10=30 0 tCLCH-2 tCLCL-5=15 0 1.5tCLCL-10=20 0 0 -- 10 -- 10 -- -- -- -- 10 10 ns ns ns ns ns ns ns ns ns ns
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. If either specification 2 or specification 59 is met with respect to data hold time, then the device functions correctly. 3. Testing is performed with equal loading on referenced pins. 4. The timing of this signal is the same for a read cycle, whether it is configured to be DEN or DS.
Am186TMCC Communications Controller Data Sheet
59
T4
T1 14
T2
T3 1 2 tw
T4
CLKOUT 66 68 A19-A0 3 S61 23 13 5 AD15-AD0 12 Addr. 15 6
8
59 24 Data 29
11 9 ALE 27 25 RD 5 BHE 67 LCS, UCS 16 MCS3-MCS0, PCS7-PCS0 19 DEN, DS 22 DT/R 3 S2-S0 4 22 20 21 18 4 26 17 10 28
Notes: 1. S6 is not valid for the first fetch until the timing for parameter 3 (status active delay (tCHSV)) is met.
Figure 17. Read Cycle Waveforms
60
Am186TMCC Communications Controller Data Sheet
Table 12.
Parameter No. 3 4 5 6 7 8 9 10 11 12 13 14 16 17 Symbol tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLCSV tCXCSX Description Status active delay Status and BHE inactive delay AD address and BHE valid delay Address hold Data valid delay Status hold time ALE active delay ALE width ALE inactive delay AD address valid to ALE Low2 AD address hold from ALE inactive AD address valid to clock High MCS/PCS active delay MCS/PCS hold from command inactive MCS/PCS inactive delay DEN inactive to DT/R2, 3 Control active delay 13,4 DS inactive delay3,4 ALE High to address valid
Write Cycle Timing1
Preliminary 50 MHz (Commercial Only) Max 12 12 12 -- 12 -- 12 -- 12 -- -- -- 12 -- Min 0 0 0 0 0 0 -- tCLCL - 5 = 15 -- 0.5 * tCLCH tCHCL 0 0 tCLCH 10 -- 10 -- -- -- 10 -- Max 10 10 10 -- 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
25 MHz Min 0 0 0 0 0 0 -- tCLCL - 10 = 30 -- 0.5 * tCLCH tCHCL 0 0 tCLCH Max 20 20 20 -- 20 -- 20 -- 20 -- -- -- 20 --
40 MHz Min 0 0 0 0 0 0 -- tCLCL - 5 = 20 -- 0.5 * tCLCH tCHCL 0 0 tCLCH
Unit
General Timing Responses
18 19 20 21 23
tCHCSX tDXDL tCVCTV tCVDEX tLHAV
0 -1 0 0 15
20 -- 20 20 --
0 -1 0 0 7.5
12 -- 12 12 --
0 -1 0 0 5
10 -- 10 10 --
ns ns ns ns ns
Am186TMCC Communications Controller Data Sheet
61
Table 12.
Parameter No. 30 31 32 33 34 35 65 67 68 87 Symbol tCLDOX tCVCTX tWLWH tWHLH tWHDX tWHDEX tAVWL tCHCSV tCHAV tAVBL Description Data hold time Control inactive delay3,4 WR pulse width WR inactive to ALE High2 Hold data after WR2 WR inactive to DEN inactive2,3 A address valid to WR Low CLKOUT High to LCS/UCS valid CLKOUT High to A address valid A address valid to WHB, WLB Low
Write Cycle Timing1 (Continued)
Preliminary 25 MHz 40 MHz Max -- 20 -- -- -- -- -- 20 20 20 Min 0 0 2tCLCL - 10 = 40 tCLCH - 2 tCLCL - 10 = 15 tCLCH tCLCL + tCHCL - 1.25 0 0 tCHCL - 1.25 Max -- 12 -- -- -- -- -- 10 10 12 50 MHz (Commercial Only) Min 0 0 2tCLCL - 10 = 30 tCLCH - 2 tCLCL - 10 = 10 tCLCH tCLCL + tCHCL - 1.25 0 0 tCHCL - 1.25 Max -- 10 -- -- -- -- -- 10 10 10 ns ns ns ns ns ns ns ns ns ns Unit
Min 0 0 2tCLCL - 10 = 70 tCLCH - 2 tCLCL - 10 = 30 tCLCH - 3 tCLCL + tCHCL -3 0 0 tCHCL - 3
Write Cycle Timing Responses
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. Testing is performed with equal loading on referenced pins. 3. The timing of this signal is different during a write cycle depending on whether it is configured to be DEN or DS. 4. This parameter applies to the DEN, DS, WR, WHB, and WLB signals.
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Am186TMCC Communications Controller Data Sheet
T4 CLKOUT 87 68 A19-A0 3
T1 14
T2
T3
T4
tw
65
6
8
S61
23 5 AD15--AD0
12 Addr. 11
7 13 Data 34 30
9 ALE
10
33
31 20 WR 20 WHB, WLB 5 BHE 67 LCS, UCS 16 MCS3-MCS0, PCS7-PCS0 20 DEN 20 DS 20 DT/R 21 4 31 32
35 17
18 31 19
31 3 S2-S0 4
Notes: 1. S6 is not valid for the first fetch until the timing for parameter 3 (status active delay (tCHSV)) is met.
Figure 18.
Write Cycle Waveforms
Am186TMCC Communications Controller Data Sheet
63
Table 13. Software Halt Cycle Timing1
Preliminary Parameter No. 3 4 5 9 10 11 19 22 68 Symbol Description tCHSV tCLSH tCLAV tCHLH tLHLL tCHLL tDXDL tCHCTV tCHAV Status active delay Status inactive delay AD address invalid delay ALE active delay ALE width ALE inactive delay DEN inactive to DT/R Low2 Control active delay 23 CLKOUT High to A address invalid 25 MHz Min 0 0 0 -- tCLCL - 10 = 30 -- -1 0 0 Max 20 20 20 20 -- 20 -- 20 20 40 MHz Min 0 0 0 -- tCLCL - 5 = 20 -- -1 0 0 Max 12 12 12 12 -- 12 -- 12 12 50 MHz (Commercial Only) Min 0 0 0 -- tCLCL - 5 = 15 -- -1 0 0 10 10 Max 10 10 10 10 -- 10 ns ns ns ns ns ns ns ns ns Unit
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. Testing is performed with equal loading on referenced pins. 3. This parameter applies to the DEN/DS signal.
T4 CLKOUT 68 A19-A0 5 S6, AD15-AD0
T1
T2
TI
TI
Invalid Address
Invalid Address 11 9 10
ALE
22 19 DEN, DS DT/R 3 S2-S0 4
Figure 19.
Software Halt Cycle Waveforms
64
Am186TMCC Communications Controller Data Sheet
Table 14. Peripheral Timing1,
Parameter No. 53 54 55 56 Symbol tINVCH tCLTMV tCHQ0SV tCHQ1SV Description Peripheral setup time Timer output delay Queue status 0 output delay Queue status 1 output delay
2
Preliminary 25 MHz Min 10 -- -- -- Max -- 25 25 25 40 MHz Min 5 -- -- -- Max -- 15 15 15 50 MHz (Commercial Only) Min 5 -- -- -- Max -- 12 12 12 ns ns ns ns Unit
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. PIO outputs change anywhere from the beginning of T3 to the first half of T4 of the bus cycle in which the PIO data register is written.
56 53 CLKOUT INT8-INT0, NMI, TMRINx DRQ0, DRQ1 TMROUT QS0 QS1 54 55
Figure 20.
Peripheral Timing Waveforms
Am186TMCC Communications Controller Data Sheet
65
Table 15. Reset Timing1
Preliminary Parameter No. 57 61 Symbol tRESIN tCLRO Description RES setup time Reset delay 25 MHz Min 10 -- Max -- 18 40 MHz Min 5 -- Max -- 15 50 MHz (Commercial Only) Min 5 -- Max -- 12 ns ns Unit
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12.
57 RES CLKOUT 61 RESOUT
Notes: 1. RES must be held Low for 1 ms during power-up to ensure proper device initialization. 2. Diagram is shown for the system PLL in its 2x mode of operation. 3. Diagram assumes that VCC is stable (i.e., 3.3 V 0.3 V) during the 1-ms RES active time.
Figure 21. Reset Waveforms
66
Am186TMCC Communications Controller Data Sheet
RES CLKOUT All Pinstrap Pins1, 2 AD15-AD01 All Other Outputs RESOUT
Notes: 1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes. 2. For a list of all the pinstraps, refer to Table 31, "Reset Configuration Pins (Pinstraps)," on page A-10.
Figure 22.
Signals Related to Reset (System PLL in 1x or 2x Mode)
RES CLKOUT
All Pinstrap Pins1, 2 AD15-AD01 All Other Outputs RESOUT
Notes: 1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes. 2. For a list of all the pinstraps, refer to Table 31, "Reset Configuration Pins (Pinstraps)," on page A-10.
Figure 23.
Signals Related to Reset (System PLL in 4x Mode)
Am186TMCC Communications Controller Data Sheet
67
Table 16. External Ready Cycle Timing1
Preliminary Parameter No. 47 48 49 50 51 52 Symbol tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL Description SRDY transition setup time2 SRDY transition hold time ARDY active hold time ARDY setup time
2 2 2
25 MHz Min 10 3 10 4 10 15 Max -- -- -- -- -- --
40 MHz Min 5 2 5 3 5 5 Max -- -- -- -- -- --
50 MHz (Commercial Only) Min 5 2 5 3 5 5 Max -- -- -- -- -- --
Unit
Ready Timing Requirements ns ns ns ns ns ns
ARDY resolution transition setup time3 ARDY inactive holding time
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. This timing must be met to guarantee proper operation. 3. This timing must be met to guarantee recognition at the clock edge.
Case 11 Case 21 Case Case CLKOUT 31 42
Tw T3 T2 T1 T1
Tw Tw T3 T2 T2 47 48
Tw Tw Tw T3 T3
T4 T4 T4 Tw T4 T4
Case 51
Note 1 SRDY Note 2
Notes: 1. Normally not ready system. 2. Normally ready system.
Figure 24. Synchronous Ready Waveforms
68
Am186TMCC Communications Controller Data Sheet
Case 11 Case 2
1 1
Tw T3 T2 T1 T1
Tw Tw T3 T2 T2
Tw Tw Tw T3 T3 50
T4 T4 T4 Tw T4 T4
Case 3
Case 42 Case 51 CLKOUT ARDY1 (Normally Not-Ready System) ARDY2 (Normally Ready System)
49 49 51 52 50
Notes: 1. In a normally not ready system, wait states are added after T3 until tARYCH and tCLARX are met. 2. In a normally ready system, a wait state is added if tARYCH and tARYCHL during T2 or tARYLCL and tCLARX during T3 are met.
Figure 25.
Asynchronous Ready Waveforms
Table 17. Bus Hold Timing1
Preliminary Parameter No. 5 15 18 58 62 63 64 Symbol tCLAV tCLAZ tCHCSX tHVCL tCLHAV tCHCZ tCHCV Description AD address valid delay AD address float delay MCSx/PCSx inactive delay HOLD setup2 HLDA valid delay Command lines float delay Command lines valid delay (after float) 25 MHz Min 0 0 0 10 0 -- -- Max 20 20 20 -- 20 20 25 40 MHz Min 0 0 0 5 0 -- -- Max 12 12 12 -- 12 12 12 50 MHz (Commercial Only) Min 0 0 0 5 0 -- -- Max 10 10 10 -- 10 10 10 ns ns ns ns ns ns ns Unit
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. This timing must be met to guarantee recognition at the next clock.
Am186TMCC Communications Controller Data Sheet
69
Case 1 Case 2 CLKOUT 58 HOLD
Ti T4
Ti Ti
Ti Ti
62 HLDA 15 AD15-AD0, DEN 18 MCS3-MCS0, PCS7-PCS0 A19-A0, S6, RD, WR, BHE, DT/R, S2-S0, WHB, WLB, UCS, LCS, ALE 63
Figure 26. Entering Bus Hold Waveforms
Case 1 Case 2 CLKOUT 58 HOLD
Ti Ti
Ti Ti
Ti T4
T1 T1
62 HLDA AD15-AD0, DEN MCS3-MCS0), PCS7-PCS0) A19-A0, S6, RD, WR, BHE, DT/R, S2-S0, WHB, WLB, UCS, LCS, ALE 64 5
Figure 27.
Exiting Bus Hold Waveforms
70
Am186TMCC Communications Controller Data Sheet
Table 18.
Parameter No. 36 37 38 39 40 Symbol tCKIN tCLCK tCHCK tCKHL tCKLH Description X1 period2 X1 Low time (1.5 V) X1 High time (1.5 V) X1 fall time (3.5 to 1.0 V) X1 rise time (1.0 to 3.5 V) X1 period2 X1 Low time (1.5 V) X1 High time (1.5 V) X1 fall time (3.5 to 1.0 V) X1 rise time (1.0 to 3.5 V) X1 period2 X1 Low time (1.5 V) X1 High time (1.5 V) X1 fall time (3.5 to 1.0 V) X1 rise time (1.0 to 3.5 V) CLKOUT period CLKOUT Low time (CL = 50 pF) CLKOUT High time (CL = 50 pF) CLKOUT rise time (1.0 to 3.5 V) CLKOUT fall time (3.5 to 1.0 V) X1 to CLKOUT skew 80 35 35 -- --
System Clocks Timing1
Preliminary 50 MHz (Commercial Only) Max 125 -- -- 5 5 Min 80 35 35 -- -- Max 125 -- -- 5 5 ns ns ns ns ns
25 MHz Min Max
40 MHz Min 100 45 45 -- --
Unit
CLKIN Requirements for 4x PLL Mode Not Supported
CLKIN Requirements for 2x PLL Mode 36 37 38 39 40 tCKIN tCLCK tCHCK tCKHL tCKLH 125 -- -- 5 5 50 20 20 -- -- 125 -- -- 5 5 40 15 15 -- -- 125 -- -- 5 5 ns ns ns ns ns
CLKIN Requirements for 1x PLL Mode 36 37 38 39 40 tCKIN tCLCK tCHCK tCKHL tCKLH 40 15 15 -- -- 60 -- -- 5 5 25 7.5 7.5 -- -- 60 -- -- 5 5 Not Supported ns ns ns ns ns
CLKOUT Timing3 42 43 44 45 46 69 tCLCL tCLCH tCHCL tCH1CH2 tCL2CL1 tCICO 40 0.5tCLCL-2 =18 0.5tCLCL-2 =18 -- -- -- -- -- -- 3 3 10 25 0.5tCLCL-1.25 =11.25 0.5tCLCL-1.25 =11.25 -- -- -- -- -- -- 3 3 10 20 0.5tCLCL-1 = 9 0.5tCLCL-1 = 9 -- -- -- -- -- -- 3 3 10 ns ns ns ns ns ns
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. Testing is performed with equal loading on referenced pins. 3. The PLL requires a maximum of 1 ms to achieve lock after all other operating conditions (VCC) are stable, which is normally achieved by holding RES active for at least 1 ms.
Am186TMCC Communications Controller Data Sheet
71
X2
36 37 38
X1
40 39 46 45
CLKOUT
69 42 44 43
Figure 28. System Clock Timing Waveforms--Active Mode (PLL 1x Mode)
Table 19.
Parameter No. 1 2 3 4 5 1 2 3 4 5 Symbol tUCKIN tUCLCK tUCHCK tUCKHL tUCKLH tUCKIN tUCLCK tUCHCK tUCKHL tUCKLH Description USBX1 period USBX1 Low time (1.5 V) USBX1 High time (1.5 V) USBX1 fall time (3.5 to 1.0 V) USBX1 rise time (1.0 to 3.5 V) USBX1 period USBX1 Low time (1.5 V) USBX1 High time (1.5 V) USBX1 fall time (3.5 to 1.0 V) USBX1 rise time (1.0 to 3.5 V)
USB Clocks Timing1
Preliminary 48 MHz Min 80 35 35 -- -- 40 15 15 -- -- Max 85 -- -- 5 5 42 -- -- 5 5 ns ns ns ns ns ns ns ns ns ns Unit
CLKIN Requirements for 4x PLL Mode
CLKIN Requirements for 2x PLL Mode
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12.
USBX2 1 USBX1 4 5 2 3
Figure 29. USB Clock Timing Waveforms
72
Am186TMCC Communications Controller Data Sheet
Table 20.
Parameter No. 1 2 3 4 5 6 7 8 9 10 11 Symbol tWH tWL tSF tFH tFD tWFH tDSC tDSF tDHC tSD tHD Description Pulse width High Pulse width Low Frame setup Frame hold/clock Frame delay/clock Frame width High Data delay/clock Data delay/FSC Data hold/clock Data setup Data hold
GCI Bus Timing1
Preliminary Min 240 240 70 20 0 130 -- -- 702 tWH + 20 50 Max -- -- -- -- -- -- 1002 1002 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. CL = 150 pF.
10 7 GCI_DCL_A 5 1 3 4 9 11 2
6 GCI_FSC_A GCI_DD_A 8
GCI_DU_A
Figure 30.
GCI Bus Waveforms
Am186TMCC Communications Controller Data Sheet
73
Table 21. PCM Highway Timing (Timing Slave)1,
Parameter No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol tCLKP tWH tWL tHCF tDZF tDZF tSUFC tDCD tSUDC tHCD tDCT tDFT tDCLT tHFI tSYNSS tWSYN tDTW3 tDTZ Description PCM clock period PCM clock High PCM clock Low Hold time from CLK Low to FSC valid Delay time to valid TXD from CLK Delay time to valid TXD from FSC Setup time for FSC High to CLK Low Delay time from CLK High to TXD valid Setup time from RXD valid to CLK Hold time from CLK Low to RXD invalid Delay to TSC valid from CLK Delay to TSC valid from FSC Delay from CLK Low of last bit to TSC invalid Hold time from CLK Low to FSC invalid Time between successive synchronization pulses FSC width invalid Delay from last bit CLK Low to TXD weak drive Delay from last bit CLK (plus 1) High to TXD disable
2
Preliminary Min 200 80 80 0 1 1 35 1 35 5 1 1 1 0 16 8 1 1 Max -- -- -- -- 25 25 -- 25 -- -- 25 25 25 -- -- -- 25 25
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK ns ns
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. TXD becomes valid after the CLK rising edge or FSC enable, whichever is later. 3. During the second half of the last bit transmittal, TXD is driven weak so that other devices can safely drive during this time.
74
Am186TMCC Communications Controller Data Sheet
15 1 7 4
PCM_CLK_x
16 8 14 2 2 3 3 10 4 9 17 n n+1 18
6 5 1
PCM_FSC_x PCM_TXD_x PCM_RXD_x 11 PCM_TSC_x 12
13
Notes: Note that the PCM_TXD_x outputs three-state. In the signal description and pin list summary tables, PCM_TXD_x is listed as O-LS-OD (totem pole output/programmable to hold last state of pin/open drain output) because of the following design characteristic. On the last bit to be transmitted in PCM highway mode, PCM_TXD_x will be driven normally during the first 1/2 bit time. During the last 1/2 bit time of the last bit of the transmission, PCM_TXD_x control will be in the hold-last-state condition (LS). In this condition, the output is driven, but at a much weaker strength. This permits another device (external to the microcontroller) to start driving during this time without bus contention problems. After this 1/2 bit time of hold-last-state condition, the PCM_TXD_x pin will be fully three-stated. In some applications, several PCM highway devices may have their PCM_TXD pins tied together. The time slot assigners should be programmed so that only one device is active at any time. The PCM_TSC_x signal permits external bus drivers, possibly to go external to the board. Each PCM_TSC_x signal is opendrain so that multiple PCM_TSC_x pins can be connected together. For example, two AM186CC microcontrollers could be connected on the same PCM highway and (with proper configuration of the time slot assigners) could occupy different time slots. An external bus driver would need to be active for both AM186CC time slots. The open drain on the PCM_TSC_x pins permits them to be wired together to achieve this.
Figure 31.
PCM Highway Waveforms (Timing Slave)
Am186TMCC Communications Controller Data Sheet
75
Table 22.
No. 1 2 Symbol tDCFH tDCFL Description
PCM Highway Timing (Timing Master)1
Preliminary Min 0 0 Max 30 30 Unit ns ns
Parameter Delay time from CLK High to FSC High Delay time from CLK High to FSC Low
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12.
1 PCM_CLK_x
2
PCM_FSC_x
Figure 32.
PCM Highway Waveforms (Timing Master)
76
Am186TMCC Communications Controller Data Sheet
Table 23. DCE Interface Timing1,
Parameter No. 1 2 3 4 5 6 7 Symbol tTCLKPER tTCLKH tTCLKL tTCLKO tTCLKSU tTCLKHD tTCLKR Description DCE clock period DCE clock High DCE clock Low DCE clock to output delay DCE clock setup DCE clock hold DCE clock rise/fall
2
Preliminary Min 95 40 40 1 15 5 -- Max -- -- -- 20 -- -- 10
Unit ns ns ns ns ns ns ns
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. Timings are shown with TCLK and RCLK in the default mode without the optional clock inversion.
7 DCE_TCLK_x 1 2 3
7
DCE_TXD_x
4
4
5 DCE_CTS_x
6
Figure 33.
DCE Transmit Waveforms
7 DCE_RCLK_x 1 2 3
7
DCE_RXD_x
5
6
5
DCE_RTR_x
4
4
Figure 34.
DCE Receive Waveforms
Am186TMCC Communications Controller Data Sheet
77
Table 24.
Parameter No. 1 2 3 4 Symbol tR tF tJR1 tJR2 Description Rise time (Cl = 50 pF) Fall time (Cl = 50 pF)
USB Timing1,
2
Preliminary 48 MHz Min 4 4 -18.5 -9 Max 20 20 18.5 9
Unit
ns ns ns ns
Consecutive transition jitter (measured at crossover point) Paired transition jitter (measured at crossover point)
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12. 2. Parameters 3 (tJR1) and 4 (tJR2) show jitter for the receiver, not the transmitter. See the USB Version 1.0 specification for more details.
Rise Time Differential Data Lines (D+/D-) 10% 1 90%
Fall Time
10% 2
Figure 35. USB Data Signal Rise and Fall Times
CLK 3 D+/D- Consecutive Transition Paired Transition 4
Figure 36. USB Receiver Jitter Tolerance
78
Am186TMCC Communications Controller Data Sheet
Table 25.
Parameter No. 1 2 3 4 5 Symbol tCLEV tCLSL tDVSH tSHDX tSLDV Description CLKOUT Low to SDEN valid CLKOUT Low to SCLK Low Data valid to SCLK High SCLK High to data invalid SCLK Low to data valid
SSI Timing1
Preliminary 25 MHz Min 0 0 10 3 -- Max 20 20 -- -- 20 40 MHz Min 0 0 5 2 -- Max 12 15 -- -- 12 50 MHz (Commercial Only) Min 0 0 5 2 -- Max 10 12 -- -- 10 ns ns ns ns ns Unit
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12.
CLKOUT 1 SDEN 2 2 SCLK 4 SDATA (RX) 5 SDATA (TX) 3
Notes: 1. SDEN is configured to be active High. 2. SCLK is configured to be CLKOUT/2. 3. Waveforms are shown for "normal" clock mode (i.e., transmit on negative edge of SCLK and receive on positive edge of SCLK).
Figure 37. Synchronous Serial Interface Waveforms
Am186TMCC Communications Controller Data Sheet
79
Table 26.
Parameter No. 1 2 5 7 15 20 25 27 30 31 68 402 403 404 Symbol tDVCL tCLDX tCLAV tCLDV tCLAZ tCVCTV tCLRL tCLRH tCLDOX tCVCTX tCHAV tCOLV tCHRAS tCHCAS Data in hold AD address valid delay Data valid delay AD address float delay Control active delay 1 RD active delay RD inactive delay Data hold time Control inactive delay CLKOUT High to A address valid Column address valid delay Change in RAS delay Change in CAS delay Description Data in setup
DRAM Timing1
Preliminary 25 MHz Min 10 3 0 0 0 0 0 0 0 0 0 0 3 3 Max -- -- 20 20 20 20 20 20 -- 20 20 20 20 20 40 MHz Min 5 2 0 0 0 0 0 0 0 0 0 0 3 3 Max -- -- 12 12 12 12 12 12 -- 12 12 12 12 12 50 MHz (Commercial Only) Min 5 2 0 0 0 0 0 0 0 0 0 0 3 3 Max -- -- 10 10 10 10 10 10 -- 10 10 10 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Notes: 1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are with the load values shown in Table 35, "Pin List Summary," on page A-12.
T4
T1
T2
T3 1
T4
2 CLKOUT 5 AD15-A0 68 A17, A15, A13, A11, A9, A7, A5, A3, A1 Row 403 RAS0, RAS1 404 CAS0, CAS1 25 RD 27 404 Addr. 402 Column 403 15 Data
Figure 38. DRAM Read Cycle without Wait-States Waveform
80
Am186TMCC Communications Controller Data Sheet
T4
T1
T2
TW
T3 1
T4
2 CLKOUT 5 AD15-AD0 68 A17, A15, A13, A11, A9, A7, A5, A3, A1 Row 403 RAS0, RAS1 404 CAS0, RAS1 25 RD 27 404 Addr. 402 Column 403 15 DATA
Figure 39. DRAM Read Cycle with Wait-States Waveform
T4
T1
T2
T3
T4
CLKOUT 5 AD15-AD0 68 Row 403 RAS0, RAS1 404 CAS0, CAS1 20 WR 31 404 Addr. 7 Data 402 Column 403 30
A17, A15, A13, A11, A9, A7, A5, A3, A1
Figure 40.
DRAM Write Cycle without Wait-States Waveform
Am186TMCC Communications Controller Data Sheet
81
T4
T1
T2
TW
T3
T4
CLKOUT 5 AD15-AD0 68 A17, A15, A13, A11, A9, A7, A5, A3, A1 RAS0, RAS1 404 CAS0, CAS1 20 WR 31 404 Row 403 Addr. 402 Column 403 7 Data 30
Figure 41.
DRAM Write Cycle with Wait-States Waveform
T4
T1
T2
TW1
TW2
TW3
T3
T4
CLKOUT 5 AD15-AD0 68 A17, A15, A13, A11, A9, A7, A5, A3, A1 Row (Invalid) 403 RAS0, RAS1 404 CAS0, CAS1 25 RD 27 404 Addr. 402 Column (Invalid) 403 15
Figure 42.
DRAM Refresh Cycle Waveform
82
Am186TMCC Communications Controller Data Sheet
APPENDIX A--PIN TABLES
This appendix contains pin tables for the AM186CC controller. Several different tables are included with the following characteristics: s Power-on reset pin defaults including pin numbers and multiplexed functions--Table 27 on page A-2. s Multiplexed page A-5. signal trade-offs--Table 28 on state, POR default operation, hold state, and voltage column--Table 35 on page A-12. For pin tables showing pins sorted by pin number and signal name, respectively, see Table 1, "PQFP Pin Assignments--Sorted by Pin Number" on page 10 and Table 2, "PQFP Pin Assignments--Sorted by Signal Name" on page 11. For s ign al de sc r ipti ons, se e Tabl e 4, " Si gna l Descriptions" on page 14. In all tables the brackets, [ ], indicate alternate, multiplexed functions, and braces, { }, indicate reset configuration pins (pinstraps). The line over a pin name indicates an active Low. The word pin refers to the physical wire; the word signal refers to the electrical signal that flows through it.
s Programmable I/O pins ordered by PIO pin number and multiplexed signal name, respectively, including pin numbers, multiplexed functions, and pin configurations following system reset--Table 29 on page A-8 and Table 30 on page A-9. s Pinstraps and page A-10. pinstrap options--Table 31 on
s Pin and signal summary showing signal name and alternate function, pin number, I/O type, maximum load values, power-on reset default function, reset
Am186TMCC Communications Controller Data Sheet
A-1
Table 27. Power-On Reset (POR) Pin Defaults
POR Default Bus Interface Unit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE ARDY BHE BSIZE8 DEN DRQ1 DT/R HLDA HOLD RD S0 S1 S2 30 31 32 36 37 42 43 44 45 49 50 64 65 69 70 84 85 88 89 90 28 34 38 46 51 66 86 92 29 35 39 47 52 67 87 93 19 14 20 94 18 105 17 98 99 97 57 56 55 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PIO33 PIO8 PIO34 -- PIO30 -- PIO29 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- {ADEN} -- -- -- -- -- -- -- {USBXCVR} -- -- Pin Number Multiplexed Signal Multiplexed Signal Multiplexed Signal PIO Pinstrap
A-2
Am186TMCC Communications Controller Data Sheet
Table 27. Power-On Reset (POR) Pin Defaults (Continued)
POR Default Pin Number 54 15 95 96 16 Multiplexed Signal -- -- -- -- -- Multiplexed Signal -- -- -- -- -- Multiplexed Signal -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PIO -- PIO35 -- -- PIO15 -- -- -- PIO13 PIO14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pinstrap -- -- -- -- -- -- -- -- -- {USBSEL1} {USBSEL2} -- -- {ONCE} -- -- -- -- -- -- -- -- -- -- -- -- -- --
S6 SRDY WHB WLB WR Chip Selects LCS 131 RAS0 -- 127 CAS1 -- MCS1 MCS2 128 CAS0 -- PCS0 5 -- -- 6 -- -- PCS1 PCS2 7 -- -- PCS3 8 -- -- 132 -- -- UCS Reset/Clocks CLKOUT 60 -- -- RES 114 -- -- RESOUT 58 -- -- USBX1 75 -- -- USBX2 76 -- -- X1 73 -- -- X2 74 -- -- Interrupts INT0 107 -- -- INT1 109 -- -- INT2 110 -- -- INT3 111 -- -- INT4 112 -- -- INT5 113 -- -- NMI 115 -- -- Synchronous Communications Interfaces Channel A (DCE) DCE_RXD_A 118 GCI_DD_A PCM_RXD_A DCE_TXD_A 119 GCI_DU_A PCM_TXD_A DCE_RCLK_A 117 GCI_DCL_A PCM_CLK_A DCE_TCLK_A 116 GCI_FSC_A PCM_FSC_A High-Speed UART/HDLC Channel D Handshaking TXD_HU 26 -- -- Debug Support QS0 62 -- -- QS1 63 -- -- Universal Serial Bus USBD+ 81 UDPLS -- USBD80 UDMNS -- PIOs PIO0 144 TMRIN1 -- PIO1 143 TMROUT1 -- PIO2 10 PCS5 -- PIO3 9 PCS4 -- PIO4 126 MCS0 --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- {CLKSEL2} {UCSX8}
Am186TMCC Communications Controller Data Sheet
A-3
Table 27. Power-On Reset (POR) Pin Defaults (Continued)
POR Default PIO5 PIO6 PIO7 PIO9 PIO10 PIO11 PIO12 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO31 PIO32 PIO36 PIO37 PIO38 PIO39 PIO40 PIO41 PIO42 PIO43 PIO44 PIO45 PIO46 PIO47 Reserved1 RSVD_104 RSVD_103 RSVD_102 RSVD_101 Pin Number 129 147 146 124 2 3 4 25 123 122 145 159 22 150 149 157 156 158 142 141 13 11 138 139 137 136 135 134 153 154 152 151 24 23 104 103 102 101 Multiplexed Signal MCS3 INT8 INT7 DRQ0 SDEN SCLK SDATA RXD_HU DCE_CTS_A DCE_RTR_A INT6 TXD_U UCLK DCE_RCLK_C DCE_TCLK_C CTS_U RTR_U RXD_U TMRIN0 TMROUT0 PCS7 PCS6 DCE_RXD_B DCE_TXD_B DCE_CTS_B DCE_RTR_B DCE_RCLK_B DCE_TCLK_B DCE_RXD_C DCE_TXD_C DCE_CTS_C DCE_RTR_C CTS_HU RTR_HU UXVRCV UXVOE UTXDMNS UTXDPLS Multiplexed Signal RAS1 PWD -- -- -- -- -- -- PCM_TSC_A -- -- DCE_TXD_D USBSOF PCM_CLK_C PCM_FSC_C DCE_TCLK_D DCE_RCLK_D DCE_RXD_D -- -- -- -- PCM_RXD_B PCM_TXD_B PCM_TSC_B -- PCM_CLK_B PCM_FSC_B PCM_RXD_C PCM_TXD_C PCM_TSC_C -- DCE_CTS_D DCE_RTR_D -- -- -- -- Multiplexed Signal -- -- -- -- -- -- -- -- -- -- -- PCM_TXD_D USBSCI -- -- PCM_FSC_D PCM_CLK_D PCM_RXD_D -- -- -- -- -- -- -- -- -- -- -- -- -- -- PCM_TSC_D -- -- -- -- -- PIO Pinstrap -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Notes: 1. For default operation and reset states, refer to Table 35, "Pin List Summary," on page A-12.
A-4
Am186TMCC Communications Controller Data Sheet
Table 28.
DESIRED FUNCTION Interface Memory SRAM LCS MCS1 MCS2 MCS3 DRAM CAS0 CAS1 RAS0 RAS1 131 127 128 129 128 127 131 129 SRAM DRAM Name Pin LOST FUNCTION Interface
Multiplexed Signal Trade-offs
Interface Name Interface Name Interface Name
Name
RAS0 CAS1 CAS0 RAS1 MCS2 MCS1 LCS MCS3
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
Synchronous Communications Interfaces DCE Channel A DCE_RXD_A DCE_TXD_A DCE_RCLK_A DCE_TCLK_A DCE_CTS_A DCE_RTR_A DCE Channel B DCE_RXD_B DCE_TXD_B DCE_RCLK_B DCE_TCLK_B DCE_CTS_B DCE_RTR_B DCE Channel C DCE_RXD_C DCE_TXD_C DCE_RCLK_C DCE_TCLK_C DCE_CTS_C DCE_RTR_C DCE Channel D DCE_RXD_D DCE_TXD_D DCE_RCLK_D DCE_TCLK_D DCE_CTS_D DCE_RTR_D PCM Channel A PCM_RXD_A PCM_TXD_A PCM_CLK_A PCM_FSC_A PCM_TSC_A PCM Channel B PCM_RXD_B PCM_TXD_B PCM_CLK_B PCM_FSC_B PCM_TSC_B 118 119 117 116 123 122 138 139 135 134 137 136 153 154 150 149 152 151 158 159 156 157 24 23 118 119 117 116 123 138 139 135 134 137 DCE Channel B DCE Channel A PCM Channel D PCM Channel C PCM Channel B PCM Channel A PCM_RXD_A PCM_TXD_A PCM_CLK_A PCM_FSC_A PCM_TSC_A -- PCM_RXD_B PCM_TXD_B PCM_CLK_B PCM_FSC_B PCM_TSC_B -- PCM_RXD_C PCM_TXD_C PCM_CLK_C PCM_FSC_C PCM_TSC_C -- PCM_RXD_D PCM_TXD_D PCM_CLK_D PCM_FSC_D PCM_TSC_D -- DCE_RXD_A DCE_TXD_A DCE_RCLK_A DCE_TCLK_A DCE_CTS_A DCE_RXD_B DCE_TXD_B DCE_RCLK_B DCE_TCLK_B DCE_CTS_B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LowSpeed UART -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RXD_U TXD_U RTR_U CTS_U -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GCI Channel A HighSpeed UART (Flow Control) CTS_HU RTR_HU GCI_DD_A GCI_DU_A GCI_DCL_A GCI_FSC_A -- -- -- -- -- -- PIO PIO -- -- -- -- -- -- GCI to PCM Conversion GCI Channel A GCI_DD_A GCI_DU_A GCI_DCL_A GCI_FSC_A -- -- -- -- -- -- -- -- -- -- PCM_CLK_C PCM_FSC_C -- -- PIO PIO PIO PIO -- -- -- -- PIO17 PIO18 PIO36 PIO37 PIO40 PIO41 PIO38 PIO39 PIO42 PIO43 PIO22 PIO23 PIO44 PIO45 PIO26 PIO20 PIO25 PIO24 PIO46 PIO47 -- -- -- -- PIO17 PIO36 PIO37 PIO40 PIO41 PIO38
Am186TMCC Communications Controller Data Sheet
A-5
Table 28.
DESIRED FUNCTION Interface PCM Channel C Name PCM_RXD_C PCM_TXD_C PCM_CLK_C PCM_FSC_C PCM_TSC_C PCM Channel D PCM_RXD_D PCM_TXD_D PCM_CLK_D PCM_FSC_D PCM_TSC_D LowSpeed UART RXD_U TXD_U RTR_U CTS_U HighSpeed UART RXD_HU TXD_HU RTR_HU CTS_HU GCI Channel A GCI_DD_A GCI_DU_A GCI_DCL_A GCI_FSC_A GCI to PCM Conversion PCM_CLK_C PCM_FSC_C 149 Pin 153 154 150 149 152 158 159 156 157 24 158 159 156 157 25 26 23 24 118 119 117 116 150 DCE Channel C DCE Channel A DCE Channel D DCE Channel D DCE Channel D Interface DCE Channel C
Multiplexed Signal Trade-offs (Continued)
Name DCE_RXD_C DCE_TXD_C DCE_RCLK_C DCE_TCLK_C DCE_CTS_C DCE_RXD_D DCE_TXD_D DCE_RCLK_D DCE_TCLK_D DCE_CTS_D DCE_RXD_D DCE_TXD_D DCE_RCLK_D DCE_TCLK_D -- -- DCE_RTR_D DCE_CTS_D DCE_RXD_A DCE_TXD_A DCE_RCLK_A DCE_TCLK_A DCE_RCLK_C DCE_TCLK_C PCM Channel C PCM Channel A PCM Channel D PCM Channel D Interface -- -- -- -- -- LowSpeed UART Name -- -- -- -- -- RXD_U TXD_U RTR_U CTS_U -- PCM_RXD_D PCM_TXD_D PCM_CLK_D PCM_FSC_D -- -- -- PCM_TSC_D PCM_RXD_A PCM_TXD_A PCM_CLK_A PCM_FSC_A PCM_CLK_C PCM_FSC_C -- -- -- -- -- -- -- -- -- -- -- -- -- -- HighSpeed UART Interface GCI to PCM Conversion Name -- -- PCM_CLK_C PCM_FSC_C -- -- -- -- -- CTS_HU -- -- -- -- -- -- -- -- -- -- -- -- -- -- PIO PIO PIO PIO PIO Interface PIO Name PIO42 PIO43 PIO22 PIO23 PIO44 PIO26 PIO20 PIO25 PIO24 PIO46 PIO26 PIO20 PIO25 PIO24 PIO16 -- PIO47 PIO46 -- -- -- -- PIO22 PIO23
LOST FUNCTION
Miscellaneous Bus Interface Clocks DEN DS UCLK USBSOF USBSCI PIOs PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 144 143 10 9 126 129 147 146 14 124 2 3 4 TMRIN1 TMROUT1 PCS5 PCS4 MCS0 MCS3 INT8 INT7 ARDY DRQ0 SDEN SCLK SDATA -- -- -- -- -- RAS1 PWD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18 18 22 22 22 Bus Interface Clocks DS DEN USBSOF UCLK UCLK -- -- Clocks -- -- USBSCI USBSCI USBSOF -- -- -- -- -- -- -- -- -- -- -- -- PIO -- -- PIO21 PIO21 PIO21
A-6
Am186TMCC Communications Controller Data Sheet
Table 28.
DESIRED FUNCTION Interface Name PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 PIO32 PIO33 PIO34 PIO35 PIO36 PIO37 PIO38 PIO39 PIO40 PIO41 PIO42 PIO43 PIO44 PIO45 PIO46 PIO47 Pin 5 6 16 25 123 122 145 159 22 150 149 157 156 158 142 141 17 18 13 11 19 20 15 138 139 137 136 135 134 153 154 152 151 24 23 Interface
Multiplexed Signal Trade-offs (Continued)
Name PCS0 PCS1 WR RXD_HU DCE_CTS_A DCE_RTR_A INT6 TXD_U UCLK DCE_RCLK_C DCE_TCLK_C CTS_U RTR_U RXD_U TMRIN0 TMROUT0 DT/R DEN PCS7 PCS6 ALE BHE SRDY DCE_RXD_B DCE_TXD_B DCE_CTS_B DCE_RTR_B DCE_RCLK_B DCE_TCLK_B DCE_RXD_C DCE_TXD_C DCE_CTS_C DCE_RTR_C CTS_HU RTR_HU Interface Name -- -- -- -- PCM_TSC_A -- -- DCE_TXD_D USBSOF PCM_CLK_C PCM_FSC_C DCE_TCLK_D DCE_RCLK_D DCE_RXD_D -- -- -- DS -- -- -- -- -- PCM_RXD_B PCM_TXD_B PCM_TSC_B -- PCM_CLK_B PCM_FSC_B PCM_RXD_C PCM_TXD_C PCM_TSC_C -- DCE_CTS_D DCE_RTR_D Interface Name -- -- -- -- -- -- -- PCM_TXD_D USBSCI -- -- PCM_FSC_D PCM_CLK_D PCM_RXD_D -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PCM_TSC_D -- Interface Name
LOST FUNCTION
Am186TMCC Communications Controller Data Sheet
A-7
Table 29.
PIO No.
PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 PIO32 PIO33 PIO34 PIO35 PIO36 PIO37 PIO38 PIO39 PIO40 PIO41 PIO42 PIO43 PIO44 PIO45 PIO46 PIO47
PIOs Sorted by PIO Number
Multiplexed Signal
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PCM_TXD_D USBSCI -- -- PCM_FSC_D PCM_CLK_D PCM_RXD_D -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PCM_TSC_D --
Pin No.
144 143 10 9 126 129 147 146 14 124 2 3 4 5 6 16 25 123 122 145 159 22 150 149 157 156 158 142 141 17 18 13 11 19 20 15 138 139 137 136 135 134 153 154 152 151 24 23
Multiplexed Signal
TMRIN1 TMROUT1 PCS5 PCS4 MCS0 MCS3 INT8 INT7 ARDY DRQ0 SDEN SCLK SDATA PCS0 PCS1 WR RXD_HU DCE_CTS_A DCE_RTR_A INT6 TXD_U UCLK DCE_RCLK_C DCE_TCLK_C CTS_U RTR_U RXD_U TMRIN0 TMROUT0 DT/R DEN PCS7 PCS6 ALE BHE SRDY DCE_RXD_B DCE_TXD_B DCE_CTS_B DCE_RTR_B DCE_RCLK_B DCE_TCLK_B DCE_RXD_C DCE_TXD_C DCE_CTS_C DCE_RTR_C CTS_HU RTR_HU
Multiplexed Signal
-- -- -- -- -- RAS1 PWD -- -- -- -- -- -- -- -- -- -- PCM_TSC_A -- -- DCE_TXD_D USBSOF PCM_CLK_C PCM_FSC_C DCE_TCLK_D DCE_RCLK_D DCE_RXD_D -- -- -- DS -- -- -- -- -- PCM_RXD_B PCM_TXD_B PCM_TSC_B -- PCM_CLK_B PCM_FSC_B PCM_RXD_C PCM_TXD_C PCM_TSC_C -- DCE_CTS_D DCE_RTR_D
Pin Configuration Following System Reset1
Input with pullup Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Alternate operation2 Input with pulldown Input with pulldown Input with pullup Input with pullup Alternate operation2 Alternate operation2 Alternate operation2 Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Alternate operation2 Alternate operation2 Input with pullup Input with pullup Alternate operation3 Alternate operation2 Alternate operation2 Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup
Notes: 1. System reset is defined as a power-on reset (i.e., the RES input pin transitioning from its Low to High state) or a reset due to a watchdog timer timeout. 2. When used as a PIO, input with pullup option available. 3. When used as a PIO, input with a pulldown option available.
A-8
Am186TMCC Communications Controller Data Sheet
Table 30.
Signal
ALE ARDY BHE CTS_HU CTS_U DCE_CTS_A DCE_CTS_B DCE_CTS_C DCE_RCLK_B DCE_RCLK_C DCE_RTR_A DCE_RTR_B DCE_RTR_C DCE_RXD_B DCE_RXD_C DCE_TCLK_B DCE_TCLK_C DCE_TXD_B DCE_TXD_C DEN DRQ0 DT/R INT6 INT7 INT8 MCS0 MCS3 PCS0 PCS1 PCS4 PCS5 PCS6 PCS7 RTR_HU RTR_U RXD_HU RXD_U SCLK SDATA SDEN SRDY TMRIN0 TMRIN1 TMROUT0 TMROUT1 TXD_U UCLK WR
PIOs Sorted by Signal Name
Multiplexed Signal
-- -- -- PCM_TSC_D PCM_FSC_D -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PCM_CLK_D -- PCM_RXD_D -- -- -- -- -- -- -- PCM_TXD_D USBSCI --
PIO No.
PIO33 PIO8 PIO34 PIO46 PIO24 PIO17 PIO38 PIO44 PIO40 PIO22 PIO18 PIO39 PIO45 PIO36 PIO42 PIO41 PIO23 PIO37 PIO43 PIO30 PIO9 PIO29 PIO19 PIO7 PIO6 PIO4 PIO5 PIO13 PIO14 PIO3 PIO2 PIO32 PIO31 PIO47 PIO25 PIO16 PIO26 PIO11 PIO12 PIO10 PIO35 PIO27 PIO0 PIO28 PIO1 PIO20 PIO21 PIO15
Pin No.
19 14 20 24 157 123 137 152 135 150 122 136 151 138 153 134 149 139 154 18 124 17 145 146 147 126 129 5 6 9 10 11 13 23 156 25 158 3 4 2 15 142 144 141 143 159 22 16
Multiplexed Signal
-- -- -- DCE_CTS_D DCE_TCLK_D PCM_TSC_A PCM_TSC_B PCM_TSC_C PCM_CLK_B PCM_CLK_C -- -- -- PCM_RXD_B PCM_RXD_C PCM_FSC_B PCM_FSC_C PCM_TXD_B PCM_TXD_C DS -- -- -- -- PWD -- RAS1 -- -- -- -- -- -- DCE_RTR_D DCE_RCLK_D -- DCE_RXD_D -- -- -- -- -- -- -- DCE_TXD_D USBSOF --
Pin Configuration Following System Reset1
Alternate operation2 Alternate operation3 Alternate operation3 Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pullup Input with pulldown Input with pullup Input with pulldown Alternate operation3 Input with pulldown Alternate operation3 Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Alternate operation3 Alternate operation3 Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Alternate operation3 Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pullup Input with pullup Alternate operation3
Notes: 1. System reset is defined as a power-on reset (i.e., the RES input pin transitioning from its Low to High state) or a reset due to a watchdog timer timeout. 2. When used as a PIO, input with a pulldown option available. 3. When used as a PIO, input with a pullup option available.
Am186TMCC Communications Controller Data Sheet
A-9
Table 31.
Signal Name {ADEN} Multiplexed Signal(s) BHE PIO34
Reset Configuration Pins (Pinstraps)1
Description Address Enable: If {ADEN} is held High or left floating during power-on reset, the address portion of the AD bus (AD15-AD0) is enabled or disabled during LCS, UCS, or other memory bus cycles based on how the software configures the DA bit setting. In this case, the memory address is accessed on the A19-A0 pins. There is a weak internal pullup resistor on {ADEN} so no external pullup is required. This mode of operation reduces power consumption. If {ADEN} is held Low on power-on reset, the AD bus drives both addresses and data, regardless of how software configures the DA bit setting. CPU PLL Mode Select 1 determines the PLL mode for the system clock source. CPU PLL Mode Select 2 is sampled on the rising edge of reset and determines the PLL mode for the system clock source. This pin has an internal pullup resistor that is active only during reset. There are four CPU PLL modes that are selected by the values of {CLKSEL1} and {CLKSEL2} as shown in Table 32. (For details on clocks see "Clock Generation and Control" on page 40.)
{CLKSEL1}
HLDA
{CLKSEL2}
[PCS4] PIO3
Table 32.
{CLKSEL1} 1 1 0 0 {ONCE} UCS {CLKSEL2} 1 0 1 0
CPU PLL Modes
CPU PLL Mode 2X, CPU PLL enabled (default) 4X, CPU PLL enabled 1X, CPU PLL enabled PLL Bypass
{UCSX8}
[MCS0] PIO4 PCS1 PIO14 PCS0 PIO13
{USBSEL2}
{USBSEL1}
ONCE Mode Request asserted Low places the AM186CC microcontroller into ONCE mode. Otherwise, the controller operates normally. In ONCE mode, all pins are threestated and remain in that state until a subsequent reset occurs. To guarantee that the controller does not inadvertently enter ONCE mode, {ONCE} has a weak internal pullup resistor that is active only during a reset. A reset ending ONCE mode should be as long as a power-on reset for the PLL to stabilize. Upper Memory Chip Select, 8-Bit Bus asserted Low configures the upper chip select region for an 8-bit bus size. This pin has a pullup resistor that is active only during reset, so no external pullup is required to set the bus to 16-bit mode. USB Clock Mode Selects 1-2 select the USB PLL operating mode. The pins have internal pullups that are active only during reset. The USB PLL can operate in one of three modes. With a crystal and the internal USB oscillator or an external oscillator, the USB PLL can output 4x or 2x the input frequency. The USB PLL can also be disabled and the USB peripheral controller can receive its clock from the CPU PLL, which is the default mode. The pins are encoded as shown in Table 33. (For details on clocks see "Clock Generation and Control" on page 40.)
Table 33. USB PLL Modes
{USBSEL1} 1 1 0 0 {USBXCVR} S0 {USBSEL2} 1 0 1 0 USB PLL Mode Use system clock (after CPU PLL mode select), USB PLL disabled (default) 4x, USB PLL enabled 2x, USB PLL enabled Reserved
USB External Transceiver Enable asserted Low disables the internal USB transceiver and enables the pins needed to hook up an external transceiver. This pin has a pullup resistor that is active only during reset, so no external pullup is required as long as the user ensures that this input is not driven Low during a power-on reset.
Notes: 1. A pinstrap is used to enable or disable features based on the state of the pin during an external reset. The pinstrap must be held in its desired state for at least 4.5 clock cycles after the deassertion of RES. The pinstraps are sampled in an external reset only (when RES is asserted), not during an internal watchdog timer-generated reset.
A-10
Am186TMCC Communications Controller Data Sheet
Pin List Table Column Definitions
The following paragraphs describes the individual columns of information in Table 35, "Pin List Summary," on page A-12. The pins are grouped alphabetically by function. Note: All maximum delay numbers should be increased by 0.035 ns for every pF of load (up to a maximum of 150 pF) over the maximum load specified in Table 35 on page A-12.
Type [] {} B H LS O OD OD-O PD PU STI
Table 34. Pin List Table Definitions
Definition Pin alternate function Pinstrap pin Bidirectional High Programmable to hold last state of pin Totem pole output Open drain output Open drain output or totem pole output Internal pulldown resistor Internal pullup resistor Schmitt trigger Input Schmitt trigger input or open drain output Three-state output
Column #1--Signal Name, [Alternate Function], {Pinstrap}
This column denotes the primar y and alternate functions of the pins. Most of the pins that have alternate functions are configured for these functions via firmware modifying values in the Peripheral Control Block. Refer to the Am186TMCC/CH/CU Microcontrollers Register Set Manual, order #21916, for full documentation of this process. Brackets, [ ], are used to indicate the alternate, multiplexed function of a pin (i.e., not power-on reset default). Braces, { }, are used to indicate the functionality of a pin only during a processor reset. These signals are called pinstraps. To select the desired configuration, the pinstraps are terminated internally with pullup resistors or externally with pulldown resistors. Their state is sampled during a processor reset and latched on the rising edge of reset. The signals must be held in the desired state for 4.5 system clock cycles after the deassertion of reset. Based on the pinstrap's state at the time they are latched, certain features of the AM186CC controller are enabled or disabled. All external termination should be implemented with 10kohm resistors on these signals. T h e pi ns tr a p s a r e l i s t e d i n Ta bl e 3 1 , " R e s e t Configuration Pins (Pinstraps)," on page A-10.
STI-OD TS
Column #4--Max Load (pF)
The Max Load column designates the capacitive load at which the I/O timing for that pin is guaranteed.
Column #5--POR Default Function
The POR Default Function column shows the status of these pins after a power-on reset. In some cases the pin is the function outlined in the "Signal Name" column of the table. The signal name is listed in the POR Default Function column if the signal is the default function and not a PIO after a processor reset. In other cases the pin is a PIO configured as an input.
Column #6--Reset State
The Reset State column indicates the termination present on the signal at reset (pullup or pulldown) and indicates whether the signal is a three-stated output or a Sc hmitt tr igger input. Refer to Table 34 for abbreviations used in this column.
Column #7--POR Default Operation
The POR Default Operation column describes the type of input and/or output that is default pin operation. Refer to Table 34 for abbreviations used in this column.
Column #2--Pin No.
The pin number column identifies the pin number of the individual I/O signal on the package.
Column #3--Type
Definitions of the abbreviations in the Type column are shown in Table 34.
Column #8--Hold State
The Hold State column shows the state of the pin in hold state. Refer to Table 34 for abbreviations used in this column.
Column #9--5 V
A "5 V" in the 5-V column indicates 5-V tolerant inputs. These inputs are not damaged and do not draw excess power when driven with levels up to VCC + 2.6 volts. These pins only drive to VCC.
Am186TMCC Communications Controller Data Sheet
A-11
Table 35.
Signal Name [Alternate Function] {Pinstrap} Bus Interface Unit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE [PIO33] ARDY [PIO8] 30 31 32 36 37 42 43 44 45 49 50 64 65 69 70 84 85 88 89 90 28 34 38 46 51 66 86 92 29 35 39 47 52 67 87 93 19 14 O O O O O O O O O O O O O O O O O O O O B B B B B B B B B B B B B B B B O STI-PD [STI] [O] STI-PU STI-PU [STI] [O] 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 50 50 Pin No. Type Max Load (pF)
Pin List Summary
POR Default Function Reset State POR Default Operation Hold State 5V
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE ARDY
TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD STI-PU
O O O O O O O O O O O O O O O O O O O O B B B B B B B B B B B B B B B B O STI-PU
TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS-PD STI
5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
A-12
Am186TMCC Communications Controller Data Sheet
Table 35. Pin List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} BHE [PIO34] {ADEN} BSIZE8 DEN [DS] [PIO30] [DRQ0] PIO9 DRQ1 DT/R [PIO29] HLDA {CLKSEL1} HOLD RD S0 {USBXCVR} S1 S2 S6 SRDY [PIO35] WHB WLB WR [PIO15] Chip Selects LCS [RAS0] [MCS0] PIO4 {UCSX8} MCS1 [CAS1] MCS2 [CAS0] [MCS3] [RAS1] PIO5 PCS0 [PIO13] {USBSEL1} PCS1 [PIO14] {USBSEL2} PCS2 131 O O O STI-PU [STI] [O] STI O O O O O O STI-PU [STI] [O] O STI-PU [STI] [O] STI O STI-PU [STI] [O] STI O 50 LCS TS-PU O TS-PU 5V Pin No. Type Max Load (pF) POR Default Function Reset State POR Default Operation Hold State 5V
20 94 18
O STI-PU [STI] [O] STI O O O STI-PU [STI] [O] STI-PD STI-PD [STI] [O] STI-PD O STI-PU [STI] [O] O STI STI O O STI O O O STI-PU STI-PU [STI] [O] O O O STI-PU [STI] [O] STI
50 50 50
BHE BSIZE8 DEN
STI-PU TS-PU TS-PU
O O O
TS-PU -- TS-PU
5V -- 5V
124 105 17 98 99 97 57 56 55 54 15 95 96 16
50 -- 50 50 -- 70 50 50 50 50 50 70 70 50
PIO9 DRQ1 DT/R HLDA HOLD RD S0 S1 S2 S6 SRDY WHB WLB WR
STI-PD STI-PD TS-PU STI-PU STI-PD TS-PU STI-PU TS-PU TS-PU TS-PD STI-PU TS-PU TS-PU STI-PU
STI-PD [STI] [O] STI-PD O O STI O O O O O STI-PU O O O
-- -- TS-PU H H TS-PU TS TS TS TS -- TS-PU TS-PU TS-PU
5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
126
50
PIO4
STI-PU
STI-PU [STI] [O]
TS-PU
5V
127 128
50 50
MCS1 MCS2
TS-PU TS-PU
O O
TS-PU TS-PU
5V 5V
129
50
PIO5
STI-PU
STI-PU [STI] [O]
TS-PU
5V
5
50
PCS0
STI-PU
O
TS-PU
5V
6 7
50 50
PCS1 PCS2
STI-PU TS-PU
O O
TS-PU TS-PU
5V 5V
Am186TMCC Communications Controller Data Sheet
A-13
Table 35. Pin List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} PCS3 [PCS4] PIO3 {CLKSEL2} [PCS5] PIO2 [PCS6] PIO32 [PCS7] PIO31 UCS {ONCE} Reset/Clocks CLKOUT RES RESOUT [UCLK] [USBSOF] [USBSCI] PIO21 USBX1 USBX2 X1 X2 Programmable Timers [TMRIN0] PIO27 [TMRIN1] PIO0 [TMROUT0] PIO28 [TMROUT1] PIO1 Interrupts INT0 INT1 INT2 INT3 INT4 INT5 [INT6] PIO19 [INT7] PIO7 107 109 110 111 112 113 145 146 STI STI STI STI STI STI STI STI-PU [STI] [O] STI STI-PU [STI] [O] -- -- -- -- -- -- 50 50 INT0 INT1 INT2 INT3 INT4 INT5 PIO19 PIO7 STI-PU STI-PU STI-PU STI-PU STI-PU STI-PU STI-PU STI-PU STI STI STI STI STI STI STI-PU [STI] [O] STI-PU [STI] [O] -- -- -- -- -- -- -- -- 5V 5V 5V 5V 5V 5V 5V 5V 142 144 141 143 STI-PU STI-PU [STI] [O] STI-PU STI-PU [STI] [O] O STI-PD [STI] [O] O STI-PD [STI] [O] 50 50 50 50 PIO27 PIO0 PIO28 PIO1 STI-PU STI-PU STI-PD STI-PD STI-PU [STI] [O] STI-PU [STI] [O] STI-PD [STI] [O] STI-PD [STI] [O] -- -- TS TS 5V 5V 5V 5V 60 114 58 O ST O STI O STI STI-PU [STI] [O] STI O STI O 70 -- 50 CLKOUT RES RESOUT -- STI H O STI O -- -- -- -- 5V 5V Pin No. 8 9 Type Max Load (pF) 50 50 POR Default Function PCS3 PIO3 Reset State TS-PU STI-PU POR Default Operation O STI-PU [STI] [O] Hold State TS-PU TS-PU 5V
O O STI-PU [STI] [O] STI O STI-PU [STI] [O] O STI-PU [STI] [O] O STI-PU [STI] [O] O STI
5V 5V
10 11 13 132
50 50 50 50
PIO2 PIO32 PIO31 UCS
STI-PU STI-PU STI-PU STI-PU
O STI-PU [STI] [O] STI-PU [STI] [O] O
TS-PU TS-PU TS-PU TS-PU
5V 5V 5V 5V
22
50
PIO21
STI-PU
STI-PU [STI] [O]
--
5V
75 76 73 74
-- -- -- --
USBX1 USBX2 X1 X2
-- -- -- --
STI O STI O
-- -- -- --
-- -- -- --
A-14
Am186TMCC Communications Controller Data Sheet
Table 35. Pin List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} [INT8] [PWD] PIO6 NMI Channel A DCE_RXD_A [GCI_DD_A] [PCM_RXD_A] DCE_TXD_A [GCI_DU_A] [PCM_TXD_A] DCE_RCLK_A [GCI_DCL_A] [PCM_CLK_A] DCE_TCLK_A [GCI_FSC_A] [PCM_FSC_A] [DCE_CTS_A] [PCM_TSC_A] PIO17 [DCE_RTR_A] PIO18 Channel B [DCE_RXD_B] [PCM_RXD_B] PIO36 [DCE_TXD_B] [PCM_TXD_B] PIO37 [DCE_RCLK_B] [PCM_CLK_B] PIO40 [DCE_TCLK_B] [PCM_FSC_B] PIO41 [DCE_CTS_B] [PCM_TSC_B] PIO38 [DCE_RTR_B] PIO39 Channel C [DCE_RXD_C] [PCM_RXD_C] PIO42 [DCE_TXD_C] [PCM_TXD_C] PIO43 153 STI STI STI-PD [STI] [O] OD-O O-LS-OD STI-PD [STI] [O] 50 PIO42 STI-PD STI-PD [STI] [O] -- 5V 138 STI STI STI-PU [STI] [O] OD-O O-LS-OD STI-PU [STI] [O] STI STI STI-PU [STI] [O] STI STI STI-PU [STI] [O] STI OD STI-PU [STI] [O] O STI-PU [STI] [O] 50 PIO36 STI-PU STI-PU [STI] [O] -- 5V 118 STI B-OD STI O-OD B-OD O-LS-OD STI STI STI STI STI STI STI OD STI-PU [STI] [O] O STI-PU [STI] [O] 50 DCE_RXD_A STI-PU STI -- 5V Pin No. Type Max Load (pF) POR Default Function Reset State POR Default Operation Hold State 5V
147 115
STI STI STI-PU [STI] [O] STI
50 --
PIO6 NMI
STI-PU STI-PU
STI-PU [STI] [O] STI
-- --
5V 5V
Synchronous Communications Interfaces
119
50
DCE_TXD_A
TS-PU
OD-O
--
5V
117
--
DCE_RCLK_A
STI-PU
STI
--
5V
116
--
DCE_TCLK_A
STI-PU
STI
--
5V
123
50
PIO17
STI-PU
STI-PU [STI] [O]
--
5V
122
30
PIO18
STI-PU
STI-PU [STI] [O]
--
5V
139
50
PIO37
STI-PU
STI-PU [STI] [O]
--
5V
135
50
PIO40
STI-PU
STI-PU [STI] [O]
--
5V
134
50
PIO41
STI-PU
STI-PU [STI] [O]
--
5V
137
50
PIO38
STI-PU
STI-PU [STI] [O]
--
5V
136
30
PIO39
STI-PU
STI-PU [STI] [O]
--
5V
154
50
PIO43
STI-PD
STI-PD [STI] [O]
--
5V
Am186TMCC Communications Controller Data Sheet
A-15
Table 35. Pin List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} [DCE_RCLK_C] [PCM_CLK_C] PIO22 [DCE_TCLK_C] [PCM_FSC_C] PIO23 [DCE_CTS_C] [PCM_TSC_C] PIO44 [DCE_RTR_C] PIO45 [RXD_U] (UART) [DCE_RXD_D] [PCM_RXD_D] PIO26 [TXD_U] (UART) [DCE_TXD_D] [PCM_TXD_D] PIO20 [CTS_U] (UART) [DCE_TCLK_D] [PCM_FSC_D] PIO24 [RTR_U] (UART) [DCE_RCLK_D] [PCM_CLK_D] PIO25 High-Speed UART [RXD_HU] PIO16 TXD_HU [CTS_HU] [DCE_CTS_D] [PCM_TSC_D] PIO46 [RTR_HU] [DCE_RTR_D] PIO47 Debug Support QS0 QS1 Universal Serial Bus USBD+ [UDPLS] USBD[UDMNS] 81 80 B STI B STI -- -- USBD+ USBDTS TS B B -- -- -- -- 62 63 O O 30 30 QS0 QS1 TS-PD TS-PD O O -- -- 5V 5V 25 26 STI STI-PU [STI] [O] O STI STI OD STI-PU [STI] [O] O O STI-PU [STI] [O] 50 30 PIO16 TXD_HU STI-PU TS-PU STI-PU [STI] [O] O -- -- 5V 5V Pin No. Type Max Load (pF) POR Default Function Reset State POR Default Operation Hold State 5V
150
STI STI-O STI-PD [STI] [O] STI STI-O STI-PD [STI] [O] STI OD STI-PU [STI] [O] O STI-PU [STI] [O] STI STI STI STI-PU [STI] [O] O OD-O O-LS-OD STI-PU [STI] [O] STI STI STI STI-PU [STI] [O] O STI STI STI-PU [STI] [O]
50
PIO22
STI-PD
STI-PD [STI] [O]
--
5V
149
50
PIO23
STI-PD
STI-PD [STI] [O]
--
5V
152
50
PIO44
STI-PU
STI-PU [STI] [O]
--
5V
151
30
PIO45
STI-PU
STI-PU [STI] [O]
--
5V
Low-Speed UART/Synchronous Communications Channel D
158
50
PIO26
STI-PU
STI-PU [STI] [O]
--
5V
159
50
PIO20
STI-PU
STI-PU [STI] [O]
--
5V
157
50
PIO24
STI-PU
STI-PU [STI] [O]
--
5V
156
30
PIO25
STI-PU
STI-PU [STI] [O]
--
5V
24
50
PIO46
STI-PU
STI-PU [STI] [O]
--
5V
23
30
PIO47
STI-PU
STI-PU [STI] [O]
--
5V
A-16
Am186TMCC Communications Controller Data Sheet
Table 35. Pin List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} [SCLK] PIO11 [SDATA] PIO12 [SDEN] PIO10 Reserved Pins RSVD_104 [UXVRCV] RSVD_103 [UXVOE] RSVD_102 [UTXDMNS] RSVD_101 [UTXDPLS] Power and Ground VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_A VCC_USB VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 12 27 40 48 59 68 78 91 106 120 125 133 148 160 77 79 1 21 33 41 53 61 71 83 100 108 121 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 104 103 102 101 -- STI -- O -- O -- O -- 50 50 50 -- -- -- -- STI-PU TS-PU PU PU -- -- -- -- -- -- -- -- -- -- -- -- Pin No. Type Max Load (pF) POR Default Function Reset State POR Default Operation Hold State 5V
Synchronous Serial Interface 3 4 2 O STI-PU [STI] [O] O STI-PU [STI] [O] O STI-PD [STI] [O] 50 50 50 PIO11 PIO12 PIO10 STI-PU STI-PU STI-PD STI-PU [STI] [O] STI-PU [STI] [O] STI-PD [STI] [O] -- -- -- 5V 5V 5V
Am186TMCC Communications Controller Data Sheet
A-17
Table 35. Pin List Summary (Continued)
Signal Name [Alternate Function] {Pinstrap} VSS VSS VSS VSS_A VSS_USB Pin No. 130 140 155 72 82 Type Max Load (pF) -- -- -- -- -- POR Default Function -- -- -- -- -- Reset State -- -- -- -- -- POR Default Operation -- -- -- -- -- Hold State -- -- -- -- -- 5V
-- -- -- -- --
-- -- -- -- --
A-18
Am186TMCC Communications Controller Data Sheet
APPENDIX B--PHYSICAL DIMENSIONS: PQR160, PLASTIC QUAD FLAT PACK (PQFP)
31.00 31.40
Pin 160
25.35 REF
27.90 28.10
Pin 120
Pin 1 I.D.
25.35 REF 27.90 28.10 31.00 31.40
Pin 40 Pin 80 3.20 3.60 3.95 MAX
0.65 BASIC
0.25 Min
SEATING PLANE
16-038-PQR-1 PQR160 12-22-95 lv
Am186TMCC Communications Controller Data Sheet
B-1
B-2
Am186TMCC Communications Controller Data Sheet
APPENDIX C--CUSTOMER SUPPORT
AMD-K6TM-2E Microprocessor AMD-K6TME Microprocessor Am5x86(R) Microprocessor Am486(R)DX Microprocessor Am386(R)SX/DX Microprocessors ElanSC300 Microcontroller AM186CC Communications Controller Am186CH HDLC Microcontroller Am186TMCU USB Microcontroller Am186ES and Am188ES Microcontrollers Am186ESLV & Am188ESLV Microcontrollers Am186ER and Am188ER Microcontrollers ElanSC410 Microcontroller ElanSC400 Microcontroller ElanSC520 Microcontroller
ElanTMSC310 Microcontroller
Am186ED Microcontroller Am186EDLV Microcontroller
Am186EM and Am188TMEM Microcontrollers Am186EMLV & Am188EMLV Microcontrollers
80C186 and 80C188 Microcontrollers 80L186 and 80L188 Microcontrollers
-- Microprocessors -- 16- and 32-bit microcontrollers -- 16-bit microcontrollers
E86TM Family of Embedded Microprocessors and Microcontrollers
Related AMD Products--E86TM Family Devices
Device 80C186/80C188 80L186/80L188 Am186TMEM/Am188TMEM Am186EMLV/Am188EMLV Am186ES/Am188ES Am186ESLV/Am188ESLV Am186ED Am186EDLV Am186ER/Am188ER AM186CC Am186CH Am186CU ElanTMSC300 ElanSC310 ElanSC400 ElanSC410 ElanSC520 Am386(R)DX Am386(R)SX Am486(R)DX Am5x86(R) AMD-K6TME AMD-K6TM-2E Description 16-bit microcontroller Low-voltage, 16-bit microcontroller High-performance, 16-bit embedded microcontroller High-performance, 16-bit embedded microcontroller High-performance, 16-bit embedded microcontroller High-performance, 16-bit embedded microcontroller High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or 16-bit external data bus High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus High-performance, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of internal RAM High-performance, 16-bit embedded communications controller High-performance, 16-bit embedded HDLC microcontroller High-performance, 16-bit embedded USB microcontroller High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller High-performance, single-chip, 32-bit embedded PC/AT microcontroller Single-chip, low-power, PC/AT-compatible microcontroller Single-chip, PC/AT-compatible microcontroller High-performance, 32-bit embedded microcontroller High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 16-bit external data bus High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 64-bit external data bus High-performance, 32-bit embedded microprocessor with 64-bit external data bus and 3DNow!TM technology
Notes:
1. 186 = 16-bit microcontroller and 80C186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit external data bus and 80C188-compatible (except where noted otherwise); LV = low voltage
Am186TMCC Communications Controller Data Sheet
C-1
Related Documents
T h e f o l l ow i n g d o c u m e n t s p r o v i d e a d d i t i o n a l information regarding the AM186CC microcontroller. s Am186TMCC/CH/CU Microcontrollers User's Manual, order #21914 s Am186TMCC/CH/CU Microcontrollers Register Set Manual, order #21916 s Am186TM and Am188TM Family Instruction Set Manual, order #21267 s Interfacing an Am186TMCC Communications Controller to an AMD SLACTM Device Using the Enhanced SSI Application Note, order #21921 Other information of interest includes: s E86TM Family Products and Development Tools CD, order #21058
UARTs, PCnet-ISA II (AMD's single-chip Ethernet solution), and several other common peripherals. The CodeKit software comes complete with instructions, royalty-free distribution rights, and software in both binary and source code formats.
Third-Party Development Support Products
T h e F u s i o n E 8 6 P r o gr a m o f Pa r t n e r s h i p s f o r Application Solutions provides the customer with an array of products designed to meet critical time-tomarket needs. Products and solutions available from the AMD FusionE86 partners include protocol stacks, emulators, hardware and software debuggers, boardlevel products, and software development tools, among others. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace.
AM186CC/CH/CU Microcontroller Customer Development Platform
The AM186CC/CH/CU customer development platform (CDP) is provided as a test and development platform for the AM186CC/CH/CU microcontrollers. The AM186CC/CH/CU CDP ships with the AM186CC microcontroller. Because this device suppor ts a superset of the features of the Am186CH HDLC and the Am186CU USB microcontrollers, the development platform can be used to evaluate the Am186CH and the Am186CU devices. The CDP is divided into two major sections: a main board and a development module. The main board serves as the primary platform for silicon evaluation and software development. The board provides connectors for accessing the major communications pe r i ph era l s, sw it ch e s to ea s il y c on fi gu r e th e microcontroller, logic analyzer, and debug headers. The development module, which attaches to the top of the main board, provides ready-to-run hardware for three of the most common communications requirements: s A 10 Mbit/s Ethernet connection s An ISDN connection (with both an S/T and a U interface) s Two POTS interfaces The CDP provides a good starting point for hardware designers, and software development can begin immediately without the normal delay that occurs while waiting for prototypes. The CDP also comes with AMD's CodeKit software that provides customers with pre-written driver software for the major communications peripherals associated with a typical Am186Cx design. Included are drivers for the HDLC channels, USB peripheral controller (for the Am186CU USB microcontroller),
Customer Service
The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86 and Comm86 family hardware and software development questions.
Note: The support telephone numbers listed below are subject to change. For current telephone numbers, refer to www.amd.com/support/literature.
Hotline and World Wide Web Support For answers to technical questions, AMD provides e-mail support as well as a toll-free number for direct access to our corporate applications hotline. The AMD World Wide Web home page provides the latest product infor mation, including technical information and data on upcoming product releases. In addition, EPD CodeKit software on the Web site provides tested source code example applications. Corporate Applications Hotline (800) 222-9323 44-(0) 1276-803-299 Toll-free for U.S. and Canada U.K. and Europe hotline
Additional contact information is listed on the back of this datasheet. For technical support questions on all E86 and Comm86 products, send e-mail to epd.support@amd.com.
C-2
Am186TMCC Communications Controller Data Sheet
World Wide Web Home Page To access the AMD home page go to: www.amd.com. Then follow the Embedded Processors link for information about E86 and Comm86 products. Questions, requests, and input concerning AMD's WWW pages can be sent via e-mail to webmaster@amd.com. Documentation and Literature Free information such as data books, user's manuals, data sheets, application notes, the E86TM Family Products and Development Tools CD, order #21058, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for product literature. Additional contact information is listed on the back of this data sheet. Literature Ordering (800) 222-9323 Toll-free for U.S. and Canada
Am186TMCC Communications Controller Data Sheet
C-3
C-4
Am186TMCC Communications Controller Data Sheet
INDEX
A
A19-A0 signals, 14 absolute maximum ratings, 45 AD15-AD0 signals, 14 address and data bus, 14, 17 address bus address bus disable in effect, 36 default operation, 35 description, 14, 17 ALE signal, 14 AM186CC controller architectural overview, 28 block diagram, 28 DC characteristics over commercial and industrial operating ranges, 46 detailed description, 28 distinctive characteristics, 1 general description, 1 I/O circuitry, 44 logic diagram by default pin function, 7 logic diagram by interface, 6 ordering information, 2 pin assignment tables, 10 pin tables (Appendix A), A-1 PQFP package, B-1 related AMD E86 family devices, C-1 signal description table, 14 static operation, 43 applications, 37 32-channel linecard system, 39 ISDN terminal adapter system, 38 ISDN to ethernet low-end router system, 38 architectural overview, 28 ARDY signal, 14 asynchronous communications asynchronous ready waveforms, 69 asynchronous serial ports (description), 31 baud clock, 43 High-Speed UART clocks, 43 High-Speed UART signal descriptions, 23 UART signal descriptions, 22
B
BHE signal, 15 block diagram, 28 BSIZE8 signal, 15 bus address bus description, 14, 17 bus hold timing, 69 bus status pins, 17 entering bus hold waveforms, 70 exiting bus hold waveforms, 70 bus interface signal list, 14
C
capacitance, 46 chip selects description, 34 ranges and DRAM configuration, 14, 20 signal descriptions, 19 CLKOUT signal, 17 clock CLKOUT signal description, 17 clock generation and control, 40 clock sharing by system and USB, 41 crystal parameters, 42 crystal selection, 42 crystal-driven clock source, 42 external clock source, 43 external interface to support clocks, 42-43 features, 40 High-Speed UART clocks, 43 PLL bypass mode, 43 suggested system clock frequencies, clock modes and crystal frequencies, 42 system and USB clock generation, 41 system clock, 40 system interfaces and clock control, 33 UART baud clock, 43 USB clock, 40 USB clock timing waveforms, 72 USB clocks timing, 72 CPU Am186 embedded CPU, 29 CPU PLL modes, A-10
Am186TMCC Communications Controller Data Sheet
Index-1
crystal crystal-driven clock source, 42 parameters, 42 selecting a crystal, 42 suggested crystal frequencies, 42 customer support documentation and literature, C-3 hotline and web, C-2 literature ordering, C-3 ordering the AM186CC controller, 2 third-party development support products, C-2 web home page, C-3
E
emulation in-circuit emulator support, 37 evaluation platform, C-2
G
GCI (general circuit interface) bus timing, 73 bus waveforms, 73 description, 31 signal descriptions, 26
D
DC characteristics over commercial and industrial operating ranges, 46 USB, 46 DCE (data communications equipment) DCE interface timing, 77 DCE receive waveforms, 77 DCE transmit waveforms, 77 signal descriptions, 23 DCE_RCLK_A signal, 23 DCE_RCLK_D signal, 25 DCE_RXD_A signal, 23 DCE_RXD_D signal, 24 DCE_TCLK_A signal, 24 DCE_TXD_A signal, 23 debug debug support signals, 19 DEN signal, 15 DMA (direct memory access) DMA request signals, 15 general-purpose DMA channels, 32 SmartDMA channels, 31 documentation, C-3 DRAM chip selects and DRAM configuration, 14 description, 34 read cycle with wait-states waveform, 81 read cycle without wait-states waveform, 80 refresh cycle waveform, 82 signal descriptions, 20 timing, 80 write cycle with wait-states waveform, 82 write cycle without wait-states waveform, 81 driver characteristics - universal serial bus, 45 DRQ1 signal, 15 DT/R signal, 15
H
HDLC (high-level data link control) channels, 31 signal descriptions, 23 High-Speed UART signal descriptions, 23 HLDA signal, 16 HOLD signal, 16 hotline and world wide web support, C-2
I
I/O I/O circuitry, 44 I/O space, 29 programmable I/O (PIO), 32 INT5-INT0 signals, 21 interrupts interrupt controller, 32 signal descriptions, 21
L
LCS signal, 19 logic diagram by default pin function, 7 logic diagram by interface, 6
M
MCS1 signal, 19 MCS2 signal, 19 memory memory organization, 29 segment register selection rules, 30 memory and peripheral interface, 33 multiplexed functions signal trade-offs, A-5
Index-2
Am186TMCC Communications Controller Data Sheet
N
NMI signal, 21
O
operating ranges, 45 ordering information, 2
power power consumption calculation, 47 power supply operation, 44 supply connections, 44 supply current, 47 typical ICC versus frequency, 47 PQFP package physical dimensions, B-1
P
package PQFP physical dimensions, B-1 PCM (pulse-code modulation) highway signal descriptions, 25 timing (timing master), 76 timing (timing slave), 74 waveforms (timing master), 76 waveforms (timing slave), 75 PCS0 signal, 20 PCS1 signal, 20 PCS2 signal, 20 PCS3 signal, 20 peripherals memory and peripheral interface, 33 peripheral timing, 65 peripheral timing waveforms, 65 system interfaces, 32 pins pin and signal tables, 9 pin assignments sorted by pin number, 10 pin assignments sorted by signal name, 11 pin connection diagram, 8 pin defaults, A-2 pin list summary, A-12 pin tables (Appendix A), A-1 pinstraps pinstraps table, A-10 PIO supply current limit, 44 PIO47-PIO0 signals, 22 PIOs (programmable I/Os) description, 32 signal descriptions, 22 sorted by pin number, A-8 sorted by signal name, A-9 PLL (phase-locked loop) modes, A-10 PLL bypass (CPU), A-10 PLL bypass mode, 43 system PLL, 40 USB PLL, 40 PLL bypass mode, 43 POR (power-on reset) pin defaults, A-2 QS1-QS0 signal, 19
Q R
RD signal, 16 read cycle timing, 58 read cycle waveforms, 60 RES signal, 18 reset definition of types, 13 power-on reset pin defaults table, A-2 signals related to reset, 67 timing, 66 waveforms, 66 reset configuration pins See pinstraps, A-10 RESOUT signal, 18 RSVD_101 pin, 18 RSVD_102 pin, 18 RSVD_103 pin, 18 RSVD_104 pin, 18
S
S0 signal, 17 S1 signal, 17 S2 signal, 17 S6 signal, 16 serial communications asynchronous serial ports, 31 description, 30 GCI, 31 HDLC, 31 SmartDMA, 31 synchronous serial port, 32 TSAs, 31 USB, 30
Am186TMCC Communications Controller Data Sheet
Index-3
signals multiplexed signal trade-offs table, A-5 pin and signal tables, 9 pin assignments sorted by signal name, 11 signal descriptions, 14 signals related to reset, 67 SmartDMA channels, 31 software halt cycle timing, 64 software halt cycle waveforms, 64 SRDY signal, 16 static operation, 43 switching characteristics and waveforms key to switching waveforms, 49 numerical key to switching parameter symbols, 54 over commercial/industrial operating ranges, 58 parameter symbols, 50 synchronous serial interface (SSI) signal descriptions, 23 synchronous ready waveforms, 68 synchronous serial port, 32 timing, 79 waveforms, 79 system system clock timing waveforms, 72 system clocks timing, 71
TSAs (time slot assigners) description, 31 TXD_HU signal, 23
U
UART, 23 asynchronous ready waveforms, 69 asynchronous serial ports (description), 31 baud clock, 43 High-Speed UART clocks, 43 High-Speed UART signal descriptions, 23 UART signal descriptions, 22 UCS signal, 20 universal serial bus driver characteristics, 45 USB clock, 40 clock timing waveforms, 72 clocks timing, 72 data signal rise and fall times, 78 description, 30 external transceiver signals, 26 PLL modes, A-10 receiver jitter tolerance, 78 signal descriptions, 26 system and USB clock generation, 41 timing, 78 USBD- signal, 26 USBD+ signal, 26 USBX1 signal, 18 USBX2 signal, 18 UTXDMNS signal, 27 UTXDPLS signal, 27 UXVOE signal, 27 UXVRCV signal, 27
T
thermal characteristics, 48 equations, 48 thermal resistance, 48 timers programmable timers, 32 signal descriptions, 22 timing asynchronous ready waveforms, 69 bus hold, 69 DCE interface, 77 DRAM, 80 external ready cycle, 68 GCI, 73 PCM highway, 74-76 peripheral timing, 65 read cycle timing, 58 reset, 66 software halt cycle, 64 SSI, 79 synchronous ready waveforms, 68 system clocks, 71 USB, 78 USB clocks, 72 write cycle timing, 61
W
watchdog timer description, 33 RES and watchdog timer reset, 18 WHB signal, 17 WLB signal, 17 WR signal, 17 write cycle timing, 61 write cycle waveforms, 63 www home page, C-3 support, C-2
Index-4
Am186TMCC Communications Controller Data Sheet
X
X1 signal, 18 X2 signal, 18
Am186TMCC Communications Controller Data Sheet
Index-5
Trademarks
E 2000 Advanced Micro Devices, Inc. All rights reserved.
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Am186TMCC Communications Controller Data Sheet

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Price & Availability of AM186CC

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